
12
5.2
RELATIONSHIP BETWEEN EXTERNAL ACCESS AND DATA BUS ..................
47
5.2.1
Relationship between External Access and Byte Enable Signals ...........
47
5.2.2
Operand Read ............................................................................................
48
5.2.3
Operand Write ............................................................................................
49
5.3
BUS CYCLES ..........................................................................................................
50
5.3.1
Bus States ..................................................................................................
50
5.3.2
Memory Access and I/O Access ...............................................................
53
5.4
CONTROL SIGNAL TIMING ...................................................................................
57
5.4.1
Bus Lock .....................................................................................................
57
5.4.2
Bus Hold .....................................................................................................
58
5.5
WRITE BUFFER......................................................................................................
59
CHAPTER 6
INTERRUPTS....................................................................................................................
61
6.1
MASKABLE INTERRUPTS .....................................................................................
61
6.2
NONMASKABLE INTERRUPTS .............................................................................
62
6.3
RESET .....................................................................................................................
62
CHAPTER 7
CLOCK CONTROLLER....................................................................................................
65
7.1
OPERATION MODES .............................................................................................
65
7.2
SLEEP MODE..........................................................................................................
66
7.3
STOP MODE ...........................................................................................................
67
7.4
PLL CONTROL REGISTER ....................................................................................
68
APPENDIX A
INSTRUCTIONS (LISTED ALPHABETICALLY).............................................................
69
APPENDIX B
INDEX ................................................................................................................................
79