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參數(shù)資料
| 型號： | μPD705100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Microprocessor(32 位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 44/81頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ΜPD705100 |
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44
V830
TM
USER'S MANUAL
4.4 WRITE BUFFER
The V830 has a four-stage write buffer (capable of holding up to 16 bytes of data).
When a store instruction is executed, the write data is buffered and written to external memory. After the
CPU has transferred data to the write buffer, the next instruction is processed. If, however, the write buffer
is full, the CPU is halted until the write cycle for the data at the head of the write buffer ends, allowing data
to be written to the write buffer. When accessing internal memory, however, instruction execution does not
stop because the write buffer is not used.
To assure the instruction execution sequence, instruction execution is halted in the following cases, not
resuming until the contents of the write buffer have all been written to external memory:
Data cache miss/hit is encountered during load instruction execution
An uncachable area is accessed during load/store instruction execution
I/O access instruction
Block transfer instruction
HALT instruction
STBY instruction
CAXI instruction
A bus hold operation (triggered by HLDRQ) is performed regardless of the state of the write buffer.
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