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CHAPTER 5 16-BIT BUS MODE
(4) Tw1 state
The bus enters the Tw1 state upon the termination of the first access in the bus cycle or when the bus
is forced to wait during a single word transfer. READY (input) is sampled at the rising edge of the bus
clock upon termination of the Tw1 state. If the sampled READY (input) is inactive, the bus re-enters the
Tw1 state. If READY (input) sampled during a read is active, data is read from the data bus and the Tw1
state ends.
(5) Tw2 state
The bus enters the Tw2 state upon the termination of the second access in the bus cycle or when the
bus is forced to wait during a single word transfer. HLDRQ (input) is sampled at the rising edge of the
bus clock in this state. READY (input) is sampled at the rising edge of the bus clock after termination
of the Tw2 state. If the sampled READY (input) is inactive, the bus re-enters the Tw1 state and the sampled
HLDRQ (input) is ignored.
If READY (input), sampled during a read, is active, data is read from the data bus and the Tw2 state
terminals. During a write, write data is output to the data bus in sync with the rising edge of the bus clock.
(6) Tb1-Tb8 states
The bus enters the Tbn state upon the termination of the n-th access to a point external to the processor,
or when it is forced to wait. READY (input) is sampled at the first rising edge of the bus clock after
termination of the state. If the sampled READY (input) is inactive, the bus re-enters the Tbn state.
If READY (input), sampled during a read, is active, the data on the data bus is read and the state
terminals. If the bus is originally in the Tb8 state, however, it enters the Ti state.
During a write in this state, write data is output in sync with the rising edge of the bus clock.
HLDRQ (input) is sampled at the rising edge of the bus clock in the last Tb8 state.
(7) Th state
The bus enters the Th state when it is held by HLDRQ (input). In this state, HLDRQ (input) is sampled
at the rising edge of the bus clock. If it is inactive, the bus enters the Ti state.