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參數(shù)資料
| 型號(hào)： | μPD705100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Microprocessor(32 位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 76/81頁(yè) |
| 文件大?。?/td> | 441K |
| 代理商： | ΜPD705100 |
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76
V830
TM
USER'S MANUAL
Instruction Operand(s)
Format
CY
OV
S
Z
Function
SAR
reg1 ,reg2
I
0
Arithmetic right shift. reg2 is arithmetically shifted
to the right by the displacement specified by the
low-order five bits of reg1 (MSB value is copied
to the MSB in sequence). The result is written
into reg2.
imm5, reg2
II
0
Arithmetic right shift. reg2 is arithmetically
shifted to the right by the displacement specified
by imm5, zero-extended to a word. The result is
written into reg2.
SATADD3
reg1, reg2,
reg3
VIII
Saturatable addition. reg1 and reg2 are added
together as signed integers.
[If no overflow has occurred:]
The result is written into reg3.
[If an overflow has occurred:]
The SAT bit is set. If the result is positive,
the positive maximum is written into reg3; if
the result is negative, the negative maximum
is written into reg3.
SATSUB3 reg1, reg2,
VIII
Saturatable subtraction. reg1 is subtracted from
reg2 as signed integers.
reg3
[If no overflow has occurred:]
The result is written into reg3.
[If an overflow has occurred:]
The SAT bit is set. If the result is positive,
the positive maximum is written into reg3; if
the result is negative, the negative maximum
is written into reg3.
SETF
imm5, reg2
II
-
-
-
-
Set flag condition. reg2 is set to 1 if the condition
specified by the low-order four bits of imm5
matches the condition flag; otherwise it is set to
0.
SHL
reg1, reg2
I
0
Logical left shift. reg2 is logically shifted to the
left (0 is put on the LSB) by the displacement
specified by the low-order five bits of reg1. The
result is written into reg2.
imm5, reg2
II
0
Logical left shift. reg2 is logically shifted to the
left by the displacement specified by imm5, zero-
extended to a word. The result is written into
reg2.
SHLD3
reg1, reg2,
reg3
VIII
-
-
-
-
Left shift of concatenation. The 64 bits
consisting of reg3 (high order) and reg2 (low
order) are logically shifted to the left by the
displacement specified by the low-order five bits
of reg1. The high-order 32 bits of the result are
written into reg3.
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