
20
V830
TM
USER'S MANUAL
1.7 INTERNAL UNITS
(1) CPU core
Executes the processing of the majority of instructions, including address calculation, arithmetic and logic
operations, and data transfer within one cycle, by means of 5-stage pipeline control.
Dedicated hardware, such as an adder with a sum-of-products function (32 bits x 32 bits + (upper/lower)
32 bits) and barrel shifter (capable of 64-bit data shift) are built in to enable the high-speed processing
of complicated instructions.
(2) Bus interface
Activates a required bus cycle according to the physical address acquired by the CPU. The bus interface
unit supports both 32-bit bus mode, in which the external data bus has a 32-bit configuration, and 16-bit
bus mode, in which it has a 16-bit configuration. It outputs appropriate control signals according to the
mode set when a bus cycle is activated.
(3) Interrupt controller
Handles received hardware interrupt requests (nonmaskable and maskable interrupt requests) . Up to
16 maskable interrupt request sources can be handled using level input. The handler for maskable
interrupts can be placed in the built-in instruction RAM.
(4) Clock controller
Creates external bus clock pulses for the interface between the CPU internal clock and the external
hardware. It also supports the halting of clock pulses to the CPU (sleep mode) as well as PLL circuit halt
(stop mode).
(5) Write buffer
Stores data write (up to four data items) when the CPU performs write to external hardware. When data
is written into the write buffer, the CPU no longer has to wait for the end of the bus cycle and can continue
processing.
(6) Internal memory
16K-byte memory. This memory consists of four 4K-byte blocks, an instruction cache, data cache,
instruction RAM, and data RAM. The instruction RAM uses direct mapping, while the data cache uses
direct mapping/write-through.