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參數(shù)資料
| 型號： | μPD705100 |
| 廠商： | NEC Corp. |
| 英文描述： | 32 Bit Microprocessor(32 位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 72/81頁 |
| 文件大小： | 441K |
| 代理商： | ΜPD705100 |
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72
V830
TM
USER'S MANUAL
Instruction Operand(s)
Format
CY
OV
S
Z
Function
CAXI
disp16
[reg1], reg2
VI
Inter-processor synchronization in multi-
processor system.
CMP
reg1, reg2
I
Comparison. reg2 is compared with reg1
sign-extended to a word and the condition flag is
set according to the result.
The comparison involves subtracting reg1 from
reg2.
imm5,
rag2
II
Comparison. reg2 is compared with imm5
sign-extended to a word and the condition flag is
set according to the result.
The comparison involves subtracting imm5,
sign-extended to a word, from reg2.
DI
II
-
-
-
-
Disable interrupt. Maskable interrupts are
disabled. DI instruction cannot disable
nonmaskable interrupts.
DIV
reg1, reg2
I
-
Division of signed operands. reg2 is divided by
reg1 (signed operands).
The quotient is stored in reg2 and the remainder
in r30. The division is performed so that the
sign of the remainder will match that of the
dividend.
DIVU
reg1, reg2
I
-
0
Division of unsigned operands. reg2 is divided
by reg1 (unsigned operands). The quotient is
stored in reg2 and the remainder in r30. The
division is performed so that the sign of the
remainder will match that of the dividend.
EI
II
-
-
-
-
Enable interrupt. Maskable interrupts are
enabled. The EI instruction cannot enable
nonmaskable interrupts.
HALT
IX
-
-
-
-
Processor halt. The processor is placed in sleep
mode.
IN.B
disp16
[reg1], reg2
VI
-
-
-
-
Port input. disp16, sign-extended to a word, is
added to reg1 to produce an unsigned 32-bit port
address. A byte of data is read from the resulting
resulting port address, zero-extended to a word,
then stored in reg2.
IN.H
disp16[reg1],
reg2
VI
-
-
-
-
Port input. disp16, sign-extended to a word, is
added to reg1 to produce an unsigned 32-bit port
address. A halfword of data is read from the
produced port address, zero-extended to a word,
and stored in reg2. Bit 0 of the unsigned
32-bit port address is masked to 0.
IN.W
disp16[reg1],
reg2
VI
-
-
-
-
Port input. disp16, sign-extended to a word, is
added to reg1 to produce an unsigned 32-bit port
address. A word of data is read from the resulting
port address, then written into reg2. Bits 0 and 1
of the unsigned 32-bit port address are masked
to 0.
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