參數資料
型號： μPD424210
廠商： NEC Corp.
英文描述： 16 bits CMOS Dynamic RAM with Optional EDO.(16M 同步動態(tài)RAM)
中文描述： 16位的CMOS動態(tài)隨機存儲器的任擇易都。（1,600同步動態(tài)RAM）的
文件頁數： 9/48頁
文件大?。?/td> 351K
代理商： ΜPD424210
μ
PD424210
9
DC Characteristics (Recommended operating conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
RAS, CAS cycling
t
RAC
= 60 ns
160
mA
1, 2, 3
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 70 ns
150
Standby current
I
CC2
RAS, CAS
≥
V
IH (MIN.)
, I
O
= 0 mA
2.0
mA
RAS, CAS
≥
V
CC
– 0.2 V, I
O
= 0 mA
1.0
RAS only refresh current
I
CC3
RAS cycling, CAS
≥
V
IH (MIN.)
t
RAC
= 60 ns
160
mA
1, 2, 3 ,4
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 70 ns
150
Operating current
I
CC4
RAS
≤
V
IL (MAX.)
, CAS cycling
t
RAC
= 60 ns
160
mA
1, 2, 5
(Hyper page mode (EDO))
t
HPC
= t
HPC (MIN.)
, I
O
= 0 mA
t
RAC
= 70 ns
150
CAS before RAS
I
CC5
RAS cycling
t
RAC
= 60 ns
160
mA
1, 2
refresh current
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 70 ns
150
Input leakage current
I
I (L)
V
I
= 0 to 5.5 V
μ
PD424210-60
μ
PD424210-70
–10
+10
μ
A
V
I
= 0 to 5.25 V
μ
PD424210-60-G
All other pins not under test = 0 V
Output leakage current
I
O (L)
V
O
= 0 to 5.5 V
μ
PD424210-60
μ
PD424210-70
–10
+10
μ
A
V
O
= 0 to 5.25 V
μ
PD424210-60-G
Output in disabled (Hi-Z)
High level output voltage
V
OH
I
O
= –5.0 mA
μ
PD424210-60
μ
PD424210-70
2.4
V
I
O
= –0.1 mA
μ
PD424210-60-G
Low level output voltage
V
OL
I
O
= +4.2 mA
μ
PD424210-60
μ
PD424210-70
0.4
V
I
O
= +0.1 mA
μ
PD424210-60-G
Notes 1.
I
CC1
, I
CC3
, I
CC4
and I
CC5
depend on cycle rates (t
RC
and t
HPC
).
2.
Specified values are obtained with outputs unloaded.
3.
I
CC1
and I
CC3
are measured assuming that address can be changed once or less during RAS
≤
V
IL (MAX.)
and CAS
≥
V
IH (MIN.)
.
4.
I
CC3
is measured assuming that all column address inputs are held at either high or low.
5.
I
CC4
is measured assuming that all column address inputs are switched only once during each hyper
page (EDO) cycle.
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