參數(shù)資料
型號： μPD424210
廠商： NEC Corp.
英文描述： 16 bits CMOS Dynamic RAM with Optional EDO.(16M 同步動態(tài)RAM)
中文描述： 16位的CMOS動態(tài)隨機(jī)存儲器的任擇易都。（1,600同步動態(tài)RAM）的
文件頁數(shù)： 14/48頁
文件大?。?/td> 351K
代理商： ΜPD424210
14
μ
PD424210
Hyper Page Mode (EDO)
Parameter
Symbol
t
RAC
= 60 ns
t
RAC
= 70 ns
Unit
Notes
MIN.
MAX.
MIN.
MAX
Read / Write cycle time
t
HPC
25
–
30
–
ns
1
RAS pulse width
t
RASP
60
125,000
70
125,000
ns
CAS pulse width
t
HCAS
10
10,000
12
10,000
ns
CAS precharge time
t
CP
10
–
10
–
ns
Access time from CAS precharge
t
ACP
–
35
–
40
ns
CAS precharge to WE delay time
t
CPWD
52
–
59
–
ns
2
RAS hold time from CAS precharge
t
RHCP
35
–
40
–
ns
Read modify write cycle time
t
HPRWC
66
–
75
–
ns
Data output hold time
t
DHC
5
–
5
–
ns
OE to CAS hold time
t
OCH
5
–
5
–
ns
4
OE precharge time
t
OEP
5
–
5
–
ns
Output buffer turn-off delay from WE
t
WEZ
0
13
0
15
ns
3,4
WE pulse width
t
WPZ
10
–
10
–
ns
4
Output buffer turn-off delay from RAS
t
OFR
0
13
0
15
ns
3,4
Output buffer turn-off delay from CAS
t
OFC
0
13
0
15
ns
3,4
Notes 1.
t
HPC (MIN.)
is applied to CAS access.
2.
If t
WCS
≥
t
WCS (MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If t
RWD
≥
t
RWD (MIN.)
, t
CWD
≥
t
CWD (MIN.)
, t
AWD
≥
t
AWD (MIN.)
and t
CPWD
≥
t
CPWD (MIN.)
, the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3.
WE: inactive (in read cycle)
CAS: inactive, OE: active ······ t
CHO
is effective.
CAS, OE: active ······ t
OCH
is effective.
4.
t
OFC (MAX.)
, t
OFR (MAX.)
and t
WEZ (MAX.)
define the time when the output achieves the conditions of Hi-Z and is
not referenced to V
OH
or V
OL
.
5.
To make I/Os to Hi-Z in read cycle, it is necessary to control RAS, CAS, WE, OE as follows. The effective
specification depends on state of each signal.
(1)
Both RAS and CAS are inactive (at the end of the read cycle)
WE: inactive, OE: active
t
OFC
is effective when RAS is inactivated before CAS is inactivated.
t
OFR
is effective when CAS is inactivated before RAS is inactivated.
(2)
Both RAS and CAS are active or either RAS or CAS is active (in read cycle)
WE, OE: inactive ······ t
OEZ
is effective.
Both RAS and CAS are inactive or RAS is active and CAS is inactive (at the end of read cycle)
WE, OE: active and either t
RRH
or t
RCH
must be met ······ t
WEZ
and t
WPZ
are effective.
The faster of t
OEZ
and t
WEZ
becomes effective.
The faster of (1) and (2) becomes effective.
相關(guān)PDF資料
PDF描述
μPD481850 Synchronous Graphics Memory (SGRAM)(8M 同步圖形存儲器)
μPD784224 16 Bit Single Chip Microcontrollers(16 位單片微控制器)
μPD784225 16 Bit Single Chip Microcontrollers(16 位單片微控制器)
μPD784225Y 16 Bit Single Chip Microcontrollers(16 位單片微控制器)
μPD78F4216Y 8/16 Bit RISC Microcontrollers(8/16位RISC微控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PD42-CAMG13 制造商:P-TEC 制造商全稱:P-tec Corporation 功能描述:Three Digit 7 Segment 0.56” Display
PD42-CAMO12 制造商:P-TEC 制造商全稱:P-tec Corporation 功能描述:Three Digit 7 Segment 0.56” Display
PD42-CAMR21 制造商:P-TEC 制造商全稱:P-tec Corporation 功能描述:Three Digit 7 Segment 0.56” Display
PD42-CAMR24 制造商:P-TEC 制造商全稱:P-tec Corporation 功能描述:Three Digit 7 Segment 0.56” Display
PD42-CAMY01 制造商:P-TEC 制造商全稱:P-tec Corporation 功能描述:Three Digit 7 Segment 0.56” Display
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*