參數(shù)資料
型號(hào)： μPD424210
廠商： NEC Corp.
英文描述： 16 bits CMOS Dynamic RAM with Optional EDO.(16M 同步動(dòng)態(tài)RAM)
中文描述： 16位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器的任擇易都。（1,600同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 13/48頁
文件大?。?/td> 351K
代理商： ΜPD424210
μ
PD424210
13
Write Cycle
Parameter
Symbol
t
RAC
= 60 ns
t
RAC
= 70 ns
Unit
Notes
MIN.
MAX.
MIN.
MAX
WE hold time referenced to CAS
t
WCH
10
–
10
–
ns
1
WE pulse width
t
WP
10
–
10
–
ns
1
WE lead time referenced to RAS
t
RWL
10
–
12
–
ns
WE lead time referenced to CAS
t
CWL
10
–
12
–
ns
WE setup time
t
WCS
0
–
0
–
ns
2
OE hold time
t
OEH
0
–
0
–
ns
Data-in setup time
t
DS
0
–
0
–
ns
3
Data-in hold time
t
DH
10
–
10
–
ns
3
Notes 1.
t
WP (MIN.)
is applied to late write cycles or read modify write cycles. In early write cycles, t
WCH (MIN.)
should
be met.
2.
If t
WCS
≥
t
WCS (MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle.
3.
t
DS (MIN.)
and t
DH (MIN.)
are referenced to the CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the WE falling edge.
Read Modify Write Cycle
Parameter
Symbol
t
RAC
= 60 ns
t
RAC
= 70 ns
Unit
Note
MIN.
MAX.
MIN.
MAX
Read modify write cycle time
t
RWC
133
–
157
–
ns
RAS to WE delay time
t
RWD
77
–
89
–
ns
1
CAS to WE delay time
t
CWD
32
–
37
–
ns
1
Column address to WE delay time
t
AWD
47
–
54
–
ns
1
Note 1.
If t
WCS
≥
t
WCS (MIN.)
, the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If t
RWD
≥
t
RWD (MIN.)
, t
CWD
≥
t
CWD (MIN.)
, t
AWD
≥
t
AWD (MIN.)
and t
CPWD
≥
t
CPWD (MIN.)
, the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
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