
CHAPTER 4 MEMORY MANAGEMENT SYSTEM
54
4.2 ADDRESS SPACES
This section describes the virtual and physical address spaces and the manner in which virtual
addresses are converted or “translated” into physical addresses in the TLB.
4.2.1 Virtual Address Space
The V
R
4101 virtual address can be either 32 or 64 bits wide, depending on whether the processor is
operating in 32-bit or 64-bit mode.
"
In 32-bit mode, addresses are 32 bits wide. The maximum user process size is 2 Gbytes (2
"
In 64-bit mode, addresses are 64 bits wide. The maximum user process size is 1 Tbyte (2
31
).
40
).
Figure 4-1 shows the translation of a virtual address into a physical address.
Figure 4-1. Virtual-to-Physical Address Translation
Virtual address
AAAA
TLB
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
The offset is then added to the PFN
passing through the TLB.
If there is a match, the page frame
number (PFN) representing the high-
order bits of the physical address is
output from the TLB.
The virtual page number (VPN) in the
virtual address (VA) is compared with
the VPN in the TLB.
TLB
entry
Physical address
3
2
1
G
ASID
Offset
VPN
Offset
PFN
As shown in Figures 4-2 and 4-3, the virtual address is extended with an address space identifier
(ASID), which reduces the frequency of TLB flushing when switching contexts. This 8-bit ASID is in the
CP0 EntryHi register, described later in this chapter. The Global (G) bit is in the EntryLo0 and EntryLo1
registers, described later in this chapter.