
CHAPTER 7 INITIALIZATION INTERFACE
141
Figure 7-7. V
R
4101 Activation Sequence (When Activation Fails)
Reset*
(Internal)
ColdReset*
(Internal)
MPOWER
CPU not activated
States of BATTINH and
GPIO[9]
i
BATTLCOK
pins are checked
Activation factor
detected
RTC
(Internal
32kHz)
PLL
(Internal)
POWERON
GPIO[9]
(BATTLOCK)
BATTINH
L
L
L
H
7.3 RESET OF THE CPU CORE
This section describes the reset sequence of the V
R
4100 CPU core. For details about factors of reset
or reset of the whole V
R
4101, refer to 7.1 and Chapter 15.
7.3.1 Cold Reset
A Cold Reset completely initializes the CPU core, except for the following register bits.
"
The TS and SR bits of the Status register are cleared to 0.
"
The ERL and BEV bits of the Status register are set to 1.
"
The upper limit value (31) is set in the Random register.
"
The Wired register is initialized to 0.
"
Bits 31 to 28 of the Config register are set to 0 and bits 22 to 3 to 0x04800; the other bits are
undefined.
"
The values of the other registers are undefined.
Once power to the processor is established, the ColdReset* (internal) and the Reset* (internal) signals
are asserted and a Cold Reset is started. After approximately 2 ms assertion, the ColdReset* signal is
deasserted synchronously with MasterOut. Then the Reset* signal is deasserted synchronously with
MasterOut, and the Cold Reset is completed.
Upon reset, the CPU core becomes bus master and drives the SysAD bus (internal). After Reset* is
deasserted, the CPU core branches to the Reset exception vector and begins executing the reset
exception code.