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CHAPTER 14 ICU (INTERRUPT CONTROL UNIT)
This chapter explains the operation of the ICU and how to set the registers of the ICU.
14.1 GENERAL
The ICU summarizes interrupt signals from each built-in peripheral unit and transfers interrupt signals
(Int0, Int1, NMI) to the CPU CORE.
The functions of the ICU are outlined below.
ADDECICU.............Performs address decode of the read/write access from the CPU to the registers
in the ICU.
REGICU.................Has the register for clock masking.
initial=0=mask. Clock is not supplied unless the CPU performs write (1) to the
register.
OUTICU .................Performs summarization after masking each interrupt (all outputs are
synchronized with the rising edge of I
mclkin). Further, controls the masking of
interrupts during the setting in the Suspend mode (doze_mskint), assert of the
int
all signal, interrupting factor summarizing signal, and the memdrv assert
timing signal at the restoration from the Suspend mode.
Interrupt requests to the CPU core are noticed by using following three signals:
NMI:
battint_intr alone.
However, switching between NMI and Int0 can be enabled by the setting on the register.
Switch to Int0 if a user intends to mask battint_intr, since NMI cannot be controlled with the
masking of interrupt by means of software.
rtc_long_intr alone.
This is exclusively used because interrupt factors such as Interval Timer require a quicker
response than that of other interrupt factors.
All other interrupts.
Refer to 14.2 for the details of interrupt factors.
Int1:
Int0: