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| 型號(hào)： | ZPSD613(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入） |
| 文件頁(yè)數(shù)： | 62/98頁(yè) |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD613(V)E1 |
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ZPSD6XX(V) Family
12-62
Power
Management
Unit
(cont.)
Page Register
The four-bit Page Register increases the addressing capability of the microcontroller by a
factor of 16. The contents of the Register can also be read by the microcontroller. The
outputs of the Page Register (PGR0-PGR3) are inputs to the ZPLD and can be included in
the EPROM or SRAM chip select equations.
Figure 30 shows the Page Register. The four Flip-Flops in the Register are connected to the
internal data bus D0–D3. The microcontroller can write to or read from the Page Register.
The Register can operate as an independent register to the microcontroller if page mode is
not implemented.
RESET
D0-D3
R/W
D0
Q0
Q1
Q2
Q3
D1
D2
D3
PAGE
REG.
PGR0
PGR1
PGR2
PGR3
DPLD
GPLD
ECSPLD
ES0-7
RS0
ZPLD
Figure 30. Page Register
Reset Input
The ZPSD6XX(V) has an active low reset input which loads internal configurations and
clear some of the registers. Figure 42 shows the reset timing requirement. The active low
range has a minimum tNLNH duration. After the rising edge of reset, the ZPSD6XX(V)
remains in the reset state during tOPR range. The device must be reset at power-up prior to
use.
While the reset input is active, the ZPLD is active and the outputs are determined by the
PSDabel equations. The chip status during reset and power down is shown in Table 34.
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