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| 型號(hào)： | ZPSD613(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入） |
| 文件頁數(shù)： | 13/98頁 |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD613(V)E1 |
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ZPSD6XX(V) Family
12-13
ZPSD6XX(V)
Architectural
Overview
(cont.)
Microcontroller Bus Interface
The ZPSD6XX(V) easily interfaces with most popular eight and sixteen-bit microcontrollers
with either multiplexed or non-multiplexed address/data busses. The device is configured to
respond to the microcontroller control signals which are also used as inputs to the ZPLDs.
Memory
The ZPSD6XX(V) contains EPROM and SRAM. The EPROM densities available are
256 Kbit, 512 Kbit and 1 Mbit. The memory space is divided into eight equally-sized blocks.
Each block can be located in a different address space defined by the user. The access
time of the EPROM includes the address latching and DPLD decoding.
The 4 Kbit SRAM may be used as a scratch pad memory and an extension of the
microcontroller SRAM. The SRAM data is retained in the event of a system power down,
provided a backup battery is connected to the Vstby pin (PC2). Switching from the V
CC
supply to standby power occurs automatically when V
CC
drops below Vstby voltage.
Page Register
The four-bit Page Register expands the address range of the microcontroller by sixteen
times. The paged address can be used as part of the address space to access external
memory and peripherals or internal EPROM, SRAM and I/O.
Power Management Unit
The Power Management Unit (PMU) in the ZPSD6XX(V) enables the user to control the
power consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity in one of two modes: the Power Down mode and Sleep mode.
Other power saving features, such as the CMiser and Turbo bits in the PMU, allow the
EPROM/SRAM/ZPLD to operate at a slower rate to conserve power.
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