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| 型號： | ZPSD613(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數(shù)： | 43/98頁 |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD613(V)E1 |
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ZPSD6XX(V) Family
12-43
I/O Ports
(cont.)
Control
Register Register Register
Setting
Setting
0
1=output,
0=input
(Note 1)
Direction
VM
Defined In
PSDabel
Declare pins only
Defined In
PSDconfiguration
NA
Mode
MCU I/O
Setting
NA
PLD I/O
Logic equations
NA
NA*
(Note 1)
NA
Data Port
(Port A,B)
NA
Specify bus type
NA
NA
NA
Address Out
(Port A,B)
Declare pins only
NA
1
1 (Note 1)
NA
Address In
(Port A,B,C)
Logic equation for
Input Micro
Cells
NA
NA
NA
NA
Peripheral I/O Logic equations
(Port A)
(PSEL0 & 1)
NA
NA
NA
PIO bit =1
Table 22. Port Operating Mode Settings
*
NA – Not Applicable
NOTE 1: The direction of the Port A, B, C pins are controlled by the Direction Register ORed with the individual
output enable product term (.oe) from the GPLD AND array.
PLD I/O Mode
The PLD I/O mode uses the port as an input to the GPLD Input Micro
Cell, and/or as an
output from the GPLD, ECSPLD. The Port assignments are shown in Tables 9 and 10. The
output can be tri-stated with a control signal defined by a product term (.oe) from the
ZPLD, or, by setting a zero in the Direction Register. The Direction Register
must not
be
set to “1” if the pin is defined as a ZPLD input pin. The PLD I/O mode is specified in
PSDabel by declaring the port pins, then writing an equation assigning it to the port.
MCU I/O Mode
In the MCU I/O Mode the microcontroller uses the ZPSD6XX(V) ports to expand its own I/O
ports. The ports on the ZPSD6XX(V) are mapped into the microcontroller address space.
The addresses of the ports are listed in Table 27.
A port pin will be put into MCU I/O mode by writing a zero to the corresponding bit in the
Control Register. The direction may be changed by writing to the Direction Register for
the port where a “1” makes it an output and a “0” an input. The output enable product
term also can change the direction of the pin (see Table 19 and 20). When the pin is
configured as output, the content of the Data Out Register drives the pins. In input mode,
the microcontroller reads the port input through the Data In buffer
Ports C and D do not have a Control Register and are in MCU I/O mode by default for pins
that are not configured as PLD I/O.
Address Out Mode
For microcontrollers with a multiplexed address/data bus, the ports in Address Out mode
drive latched addresses to external devices. Address [7:0] are always assigned to Port A.
See Table 28 for the address output pin assignments on Ports A and B. The Direction
Register and the Control Register must be set to a “1” for port pins using Address Out
mode.
In non-multiplexed 8 bit bus mode, address[7:0] are available on Port B in Address Out
Mode.
Port Operating Modes
(cont.)
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