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| 型號： | ZPSD613(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入） |
| 文件頁數(shù)： | 12/98頁 |
| 文件大?。?/td> | 484K |
| 代理商： | ZPSD613(V)E1 |
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ZPSD6XX(V) Family
12-12
ZPSD6XX(V) devices consist of several major functional blocks. Figure 1 shows the
architecture of the ZPSD6XX(V) device family. The functions of each block are described
briefly in the following sections. Many of the blocks perform multiple functions, and are user
configurable.
Zero Power PLDs
The device contains three ZPLD blocks each optimized for a different function as shown in
Table 5. The functional partitioning of the ZPLDs reduces power consumption, optimizes
cost/performance and ease of design entry.
The Decode PLD (DPLD) is used to decode and generate chip selects for the ZPSD6XX(V)
internal memory, registers and peripheral mode. The External Chip Select PLD (ECSPLD)
is optimized to generate chip selects for devices external to the ZPSD6XX(V). The General
Purpose PLD (GPLD) can implement user defined logic functions. The DPLD and ECSPLD
have combinatorial outputs while the GPLD has 12 Output Micro
Cells. The ZPSD6XX(V)
also has 23 Input Micro
Cells that can be configured as inputs to the ZPLD. The ZPLDs
receive their inputs from the ZPLD Input bus and are differentiated by their output
destinations, number of product terms, and Micro
Cells.
The ZPLDs are designed to consume minimum power by using Zero Power design
techniques. The speed and power consumption of the ZPLD is controlled by the Turbo Bit in
the PMMR0 Register that is set by the microcontroller.
I/O Ports
The ZPSD6XX(V) has 26 I/O pins divided among four ports. Each I/O pin can be
individually configured to provide many functions. Ports A, B, C and D can be configured as
standard MCU I/O ports, ZPLD I/O, or latched address outputs for microcontrollers using
multiplexed address/data busses.
Ports A and B can also be configured as a data port for microcontrollers with a
non-multiplexed bus. In these modes, Port A is connected to D0–7 and Port B to D8–15.
ZPSD6XX(V)
Architectural
Overview
Name
Abbreviation
Inputs
Outputs
Product Terms
Decode PLD
DPLD
63
12
13
External Chip Select PLD
ECSPLD
24
7
7
General PLD
GPLD
63
12
109
Table 5.
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