參數(shù)資料
型號(hào)： ZPSD613(V)E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入）
文件頁數(shù)： 57/98頁
文件大?。?/td> 484K
代理商： ZPSD613(V)E1
ZPSD6XX(V) Family
12-57
The ZPSD6XX(V) offers a number of configurable power saving options which include the
Automatic Power Down (APD) Logic and the Power Management Mode Registers (PMMR0
and PMMR1). The APD Logic allows the ZPSD6XX(V) to enter into either Power Down or
Sleep Mode automatically, while the PMMRs can be configured at run time by the
microcontroller to selectively reduce the power consumption of the PSD functional blocks.
The APD Logic and Power Down Mode
The Automatic Power Down (APD) logic puts the ZPSD6XX(V) into power savings mode by
monitoring the activity of the address strobe (ALE/AS). If the APD unit is enabled, the
four-bit APD counter starts counting whenever the address strobe is inactive. If the strobe
remains inactive for fifteen CLKIN clock periods, the power down (PDN) signal will become
active and the ZPSD6XX(V) enter into either Power Down or Sleep Mode. Immediately after
ALE starts pulsing the ZPSD6XX(V) will return to normal operation. The APD counter clock
source comes from the CLKIN pin which is pin PD1 on Port D. In order to guarantee that the
APD counter will not overflow when enabled, there should be less than 15 clocks between
two successive ALE pulses.
Usually, microcontrollers entering power down mode will freeze their ALE at logic high or
low level. By programming bit 0 of PMMR0, the APD knows when the MCU is in
power down mode. If the APD detects the ALE level is in the power down state for
15 CLKIN periods, then the ZPSD6XX(V) will enter a power down mode. To enable the APD
operation, the APD bit in the PMMR0 should be set to “1”.
When the address strobe starts pulsing again, or the CSI input switches from high to low,
the ZPSD6XX(V) will return to normal activity.
When the PDN signal is set to “1” (active state) in Power Down (or Sleep Mode), the
ZPSD6XX(V) MCU bus interface is disabled and all MCU inputs (address, data and control
signals) are blocked from entering the device. If the clock input to the ZPLD is not needed
in Power Down mode, it should be blocked to save power by setting Bit 4 and 5 in the
PMMR0 to “1”.
The ZPLD Power Management
The ZPLD implements a Zero Power Mode, which provides considerable power savings
for low to medium frequency operations. To enable this feature, the ZPLD Turbo bit in the
Power Management Mode Register 0 (PMMR0) has to be turned off.
If none of the inputs to the ZPLD are switching for a time period of 70 ns, the ZPLD puts
itself into Zero Power Mode and the current consumption is minimal. The ZPLD will resume
normal operation as soon as one or more of the inputs change state.
Two other features of the ZPLD provide additional power savings:
1. Clock Disable:
Users can disable the clock input to the ZPLD and/or macrocells, thereby reducing AC
power consumption.
2. Product Term Disable:
Unused product terms in the ZPLD are disabled by the PSDsoft Software automatically
for further power savings.
Power
Management
Unit
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