
XRT86SH221
PRELIMINARY
167
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
REV. P1.0.5
BIT 3 - Detection of Pointer Increment Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Detection of Pointer Increment Interrupt has occurred
since the last read of this register. If this interrupt is enabled, then the Receive STM-0 POH Processor block will
generate an interrupt anytime it detects a Pointer Increment event.
0 - Indicates that the Detection of Pointer Increment interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Detection of Pointer Increment interrupt has occurred since the last read of this register.
BIT 2 - Detection of NDF Pointer Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Detection of NDF Pointer interrupt has occurred since
the last read of this register.
If this interrupt is enabled, then the Receive STM-0 POH Processor block will generate an interrupt anytime it detects
an NDF Pointer event.
0 - Indicates that the Detection of NDF Pointer interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Detection of NDF Pointer interrupt has occurred since the last read of this register.
BIT 1 - Change of LOP-P Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change in LOP-P Defect Condition interrupt has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive STM-0 POH Processor block will generate an interrupt in response to either
of the following events.
When the Receive STM-0 POH Processor block declares the LOP-P defect condition.
·When the Receive STM-0 POH Processor block clears the LOP-P defect condition.
0 - Indicates that the Change in LOP-P Defect Condition interrupt has NOT occurred since the last read of this
register.
1 - Indicates that the Change in LOP-P Defect Condition interrupt has occurred since the last read of this register.
N
OTE
:
The user can determine if the Receive STM-0 POH Processor block is currently declaring the LOP-P defect
condition by reading out the state of BIT 1 (LOP-P Defect Declared) within the Receive STM-0 Path - SDH
Receive POH Status - Byte 0 Register (Address Location=0x0287).
BIT 0 - Change of AIS-P Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change of AIS-P Defect Condition Interrupt has occurred
since the last read of this register.
If this interrupt is enabled, then the Receive STM-0 POH Processor block will generate an interrupt in response to either
of the following events.
Whenever the Receive STM-0 POH Processor block declares the AIS-P defect condition.
Whenever the Receive STM-0 POH Processor block clears the AIS-P defect condition.
0 - Indicates that the Change of AIS-P Defect Condition Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Change of AIS-P Defect Condition Interrupt has occurred since the last read of this register.
N
OTE
:
The user can determine if the Receive STM-0 POH Processor block is currently declaring the AIS-P defect
condition by reading out the state of BIT 0 (AIS-P Defect Declared) within the Receive STM-0 Path - SDH
Receive POH Status - Byte 0 Register (Address Location= 0x0287).