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參數(shù)資料
| 型號(hào)： | XRT86SH221 |
| 廠商： | Exar Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 11/353頁(yè) |
| 文件大小： | 2330K |
| 代理商： | XRT86SH221 |
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PRELIMINARY
XRT86SH221
VIII
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
8.1 STM-0/STM-1 TELECOM BUS INTERFACE TIMING INFORMATION.......................................................... 317
8.2 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-0 APPLICATIONS............... 317
F
IGURE
63. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
OUTPUT
VIA
THE
T
RANSMIT
STM-0/STM-1 T
ELECOM
B
US
I
NTERFACE
(
FOR
STM-0 A
PPLICATIONS
) ...................................................................................................................... 317
T
ABLE
284 T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
STM-0 T
ELECOM
B
US
I
NTERFACE
- STM-0 A
PPLICATIONS
........................... 318
8.3 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 SLOT MASTER APPLICATIONS
318
F
IGURE
64. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
OUTPUT
VIA
THE
T
RANSMIT
STM-0/STM-1 T
ELECOM
B
US
I
NTERFACE
(
FOR
STM-1 A
PPLICATIONS
) ...................................................................................................................... 318
F
IGURE
65. A
N
I
LLUSTRATION
OF
THE
TIMING
RELATIONSHIPS
BETWEEN
THE
T
X
SBFP_IN_OUT
OUTPUT
PIN
,
AND
THE
T
X
A_CLK
OUTPUT
PIN
,
WITHIN
THE
T
RANSMIT
STM-1 T
ELECOM
B
US
I
NTERFACE
(S
LOT
M
ASTER
M
ODE
A
PPLICATION
)............................... 319
T
ABLE
285 T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
STM-0/STM-1 T
ELECOM
B
US
I
NTERFACE
- STM-1 S
LOT
M
ASTER
A
PPLICATIONS
319
8.4 THE TRANSMIT STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 SLOT SLAVE APPLICATIONS
320
F
IGURE
66. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
OUTPUT
VIA
THE
T
RANSMIT
STM-0/STM-1 T
ELECOM
B
US
I
NTERFACE
(
FOR
STM-1 A
PPLICATIONS
) ...................................................................................................................... 320
F
IGURE
67. A
N
I
LLUSTRATION
OF
THE
TIMING
RELATIONSHIPS
BETWEEN
THE
T
X
SBFP
INPUT
PIN
AND
THE
T
X
A_CLK
OUTPUT
PIN
WITHIN
THE
T
RANSMIT
STM-0/STM-1 T
ELECOM
B
US
I
NTERFACE
(STM-1 S
LOT
S
LAVE
A
PPLICATIONS
) ........................................... 320
T
ABLE
286 T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
STM-0/STM-1 T
ELECOM
B
US
I
NTERFACE
- STM-1 S
LOT
S
LAVE
A
PPLICATIONS
321
8.5 THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-0 APPLICATIONS.................. 321
F
IGURE
68. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
I
NPUT
VIA
THE
R
ECEIVE
STM-0/STM-1 T
ELECOM
B
US
I
N
-
TERFACE
..................................................................................................................................................................... 321
T
ABLE
287 T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STM-0/STM-1 T
ELECOM
B
US
I
NTERFACE
- STM-0 A
PPLICATIONS
................. 321
8.6 THE RECEIVE STM-0/STM-1 TELECOM BUS INTERFACE TIMING - STM-1 APPLICATIONS.................. 322
F
IGURE
69. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
S
IGNALS
THAT
ARE
I
NPUT
VIA
THE
R
ECEIVE
STM-0/STM-1 T
ELECOM
B
US
I
N
-
TERFACE
..................................................................................................................................................................... 322
T
ABLE
288 T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STM-0/STM-1 T
ELECOM
B
US
I
NTERFACE
- STM-1 A
PPLICATIONS
................. 322
8.7 STM-0 LIU INTERFACE TIMING INFORMATION .......................................................................................... 323
8.7.1 RECEIVE STM-0/STM-1 LIU INTERFACE TIMING.................................................................................................... 323
F
IGURE
70. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
R
ECEIVE
STM-0/STM-1
SIGNALS
THAT
ARE
INPUT
TO
THE
R
ECEIVE
STM-0/
STM-1 LIU I
NTERFACE
B
LOCK
- S
HARED
P
ORT
........................................................................................................... 323
T
ABLE
289 T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STM-0/STM-1 LIU I
NTERFACE
WHEN
THE
R
ECEIVE
STM-0/STM-1 TOH P
ROCESSOR
BLOCK
HAS
BEEN
CONFIGURED
TO
SAMPLE
THE
R
X
STM0DATA
SIGNAL
UPON
THE
RISING
EDGE
OF
THE
R
X
STM0CLK
SIGNAL
323
8.7.2 TRANSMIT STM-0/STM-1 LIU INTERFACE TIMING................................................................................................. 324
F
IGURE
71. A
N
I
LLUSTRATION
OF
THE
W
AVEFORMS
OF
THE
STM-0/STM-1
SIGNALS
THAT
ARE
OUTPUT
FROM
THE
T
RANSMIT
STM-0/STM-
1 LIU I
NTERFACE
- D
EDICATED
P
ORT
........................................................................................................................... 324
T
ABLE
290 T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
STM-0/STM-1 LIU I
NTERFACE
WHEN
THE
T
RANSMIT
STM-0/STM-1 TOH P
ROCES
-
SOR
BLOCK
HAS
BEEN
CONFIGURED
TO
UPDATE
THE
T
X
STM0DATA
SIGNAL
UPON
THE
RISING
EDGE
OF
THE
T
X
STM0CLK
SIGNAL
324
8.8 TRANSMIT STM-0/STM-1 TOH AND POH DATA INPUT PORT ................................................................... 325
F
IGURE
72. I
LLUSTRATION
OF
T
IMING
W
AVE
-
FORM
OF
THE
T
RANSMIT
STM-0/STM-1 TOH
AND
POH O
VERHEAD
D
ATA
I
NPUT
P
ORT
325
T
ABLE
291 T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
STM-0/STM-1 TOH
AND
POH O
VERHEAD
D
ATA
I
NPUT
P
ORT
..................... 325
8.9 TRANSMIT VC-4 POH DATA INPUT PORT................................................................................................... 326
F
IGURE
73. I
LLUSTRATION
OF
T
IMING
W
AVE
-
FORM
OF
THE
T
RANSMIT
VC-4 POH D
ATA
I
NPUT
P
ORT
............................................. 326
T
ABLE
292 T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
VC-4 POH D
ATA
I
NPUT
P
ORT
..................................................................... 326
8.10 RECEIVE STM-0/STM-1 TOH AND POH DATA OUTPUT PORT................................................................ 327
F
IGURE
74. I
LLUSTRATION
OF
THE
T
IMING
W
AVE
-
FORM
OF
THE
R
ECEIVE
STM-0/STM-1 TOH
AND
POH D
ATA
O
UTPUT
P
ORT
...... 327
T
ABLE
293 T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
STM-0/STM-1 TOH
AND
POH D
ATA
O
UTPUT
P
ORT
..................................... 327
8.11 RECEIVE VC-4 POH DATA OUTPUT PORT................................................................................................ 328
F
IGURE
75. I
LLUSTRATION
OF
THE
T
IMING
W
AVE
-
FORM
OF
THE
R
ECEIVE
VC-4 POH D
ATA
O
UTPUT
P
ORT
..................................... 328
T
ABLE
294 T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
VC-4 POH D
ATA
O
UTPUT
P
ORT
................................................................... 328
8.12 INGRESS DIRECTION - ADD/DROP PORT TIMING.................................................................................... 329
8.12.1 INGRESS DIRECTION - ADD PORT TIMING .......................................................................................................... 329
F
IGURE
76. I
LLUSTRATION
OF
THE
I
NGRESS
-D
IRECTION
A
DD
P
ORT
S
IGNALS
................................................................................ 329
T
ABLE
295 T
IMING
I
NFORMATION
FOR
THE
I
NGRESS
-D
IRECTION
A
DD
P
ORT
S
IGNALS
..................................................................... 329
8.12.2 INGRESS DIRECTION - DROP PORT TIMING........................................................................................................ 330
F
IGURE
77. I
LLUSTRATION
OF
THE
I
NGRESS
-D
IRECTION
D
ROP
P
ORT
S
IGNALS
............................................................................... 330
T
ABLE
296 T
IMING
I
NFORMATION
FOR
THE
I
NGRESS
-D
IRECTION
D
ROP
P
ORT
S
IGNALS
................................................................... 330
8.13 EGRESS DIRECTION - ADD/DROP PORT TIMING..................................................................................... 331
8.13.1 EGRESS DIRECTION - ADD PORT TIMING............................................................................................................ 331
F
IGURE
78. I
LLUSTRATION
OF
THE
E
GRESS
-D
IRECTION
A
DD
P
ORT
S
IGNALS
................................................................................. 331
T
ABLE
297 T
IMING
I
NFORMATION
FOR
THE
E
GRESS
-D
IRECTION
A
DD
P
ORT
S
IGNALS
...................................................................... 331
8.13.2 EGRESS DIRECTION - DROP PORT TIMING......................................................................................................... 332
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86SH221IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH328 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH328_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH328IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL32_1 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86SH221_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU |
| XRT86SH221ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC VOYAGER LITE RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86SH221IB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SDH-TO-PDH, VT/TU INTGR 21 CHNL 2FRAME RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86SH221IB-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC SDH-TO-PDH, VT/TU INTGR 21 CHNL 2FRAME RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86SH221OR | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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