
PRELIMINARY
XRT86SH221
128
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
0 - Indicates that the Detection of B1 Byte Error Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Detection of B1 Byte Error Interrupt has occurred since the last read of this register
BIT 2 - Change of Loss of Frame (LOF) Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change of LOF Defect Condition interrupt has occurred
since the last read of this register. The Receive STM-0 TOH Processor block will generate this interrupt in response to
either of the following events.
Whenever the Receive STM-0 TOH Processor block declares the LOF Defect condition.
Whenever the Receive STM-0 TOH Processor block clears the LOF Defect condition.
0 - Indicates that the Change of LOF Defect Condition interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Change of LOF Defect Condition interrupt has occurred since the last read of this register.
N
OTE
:
The user can determine whether or not the Receive STM-0 TOH Processor block is currently declaring the LOF
defect condition by reading out the state of BIT 2 (LOF Defect Declared) within the Receive STM-0 Transport
Status Register - Byte 0 (Address Location= 0x0207).
BIT 1 - Change of SEF Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change of SEF Defect Condition Interrupt has occurred
since the last read of this register. The Receive STM-0 TOH Processor block will generate this interrupt in response to
either of the following events.
Whenever the Receive STM-0 TOH Processor block declares the SEF defect condition.
Whenever the Receive STM-0 TOH Processor block clears the SEF defect condition.
0 - Indicates that the Change of SEF Defect Condition Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Change of SEF Defect Condition Interrupt has occurred since the last read of this register.
N
OTE
:
The user can determine whether or not the Receive STM-0 TOH Processor block is currently declaring the SEF
defect condition by reading out the state of BIT 1 (SEF Defect Declared) within the Receive STM-0 Transport
Status Register - Byte 0 (Address Location= 0x0207).
BIT 0 - Change of Loss of Signal (LOS) Defect Condition Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the Change of LOS Defect Condition interrupt has occurred
since the last read of this register. The Receive STM-0 TOH Processor block will generate this interrupt in response to
either of the following events.
Whenever the Receive STM-0 TOH Processor block declares the LOS defect condition.
Whenever the Receive STM-0 TOH Processor block clears the LOS defect condition.
0 - Indicates that the Change of LOS Defect Condition Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the Change of LOS Defect Condition Interrupt has occurred since the last read of this register.
N
OTE
:
The user can determine whether or not the Receive STM-0 TOH Processor block is currently declaring the LOS
defect condition by reading out the contents of BIT 0 (LOS Defect Declared) within the Receive STM-0
Transport Status Register - Byte 0 (Address Location= 0x0207).