
PRELIMINARY
XRT86SH221
130
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
BIT 7 - New S1 Byte Value Interrupt Enable
This READ/WRITE bit-field is used to enable or disable the New S1 Byte Value Interrupt.
If this interrupt is enabled, then the Receive STM-0 TOH Processor block will generate this interrupt anytime it receives
and accepts a new S1 byte value. The Receive STM-0 TOH Processor block will accept a new S1 byte after it has
received it for 8 consecutive STM-0 frames.
0 - Disables the New S1 Byte Value Interrupt.
1 - Enables the New S1 Byte Value Interrupt.
BIT 6 - Change in S1 Byte Unstable Defect Condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change in S1 Byte Unstable Defect Condition
Interrupt..
If the user enables this bit-field, then the Receive STM-0 TOH Processor block will generate an interrupt in response to
either of the following conditions
When the Receive STM-0 TOH Processor block declares the S1 Byte Unstable defect condition
When the Receive STM-0 TOH Processor block clears the S1 Byte Unstable defect condition.
0 - Disables the Change in S1 Byte Unstable Defect Condition Interrupt.
1 - Enables the Change in S1 Byte Unstable Defect Condition Interrupt.
BIT 5 - Change in Section Trace Message Unstable defect condition Interrupt Enable
This READ/WRITE bit-field is used to either enable or disable the Change in Section Trace Message Unstable Defect
Condition Interrupt.
If this interrupt is enabled, then the Receive STM-0 TOH Processor block will generate an interrupt in response to either
of the following conditions.
Whenever the Receive STM-0 TOH Processor block declares the Section Trace Message Unstable defect
condition.
Whenever the Receive STM-0 TOH Processor block clears the Section Trace Message Unstable defect
condition.
0 - Disable the Change of Section Trace Message Unstable defect condition Interrupt.
1 - Enables the Change of Section Trace Message Unstable defect condition Interrupt.
BIT 4 - New Section Trace Message Interrupt Enable
This READ/WRITE bit-field is used to enable or disable the New Section Trace Message interrupt.
If this interrupt is enabled, then the Receive STM-0 TOH Processor block will generate this interrupt anytime it receives
and accepts a new Section Trace Message within the incoming STM-0 data-stream. The Receive STM-0 TOH
Processor block will accept a new Section Trace Message after it has received it 3 (or 5) consecutive times.
0 - Disables the New Section Trace Message Interrupt.
1 - Enables the New Section Trace Message Interrupt.
T
ABLE
58: R
ECEIVE
STM-0/STM-1 T
RANSPORT
I
NTERRUPT
E
NABLE
R
EGISTER
1 (RTIER1 = 0
X
020E)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
New S1 Byte
Interrupt
Enable
Change in
S1 Byte
Unstable
Defect Con-
ditionInter-
rupt Enable
Change in
Section
Trace Mes-
sage Unsta-
ble Defect
Condition
Interrupt
Enable
New Section
Trace Mes-
sage Inter-
rupt Enable
Change in
Section
Trace Mes-
sage Mis-
match Defect
Condition
Interrupt
Enable
Unused
Change in
K1, K2 Byte
Unstable
Defect Con-
ditionInter-
rupt Enable
New K1K2
Byte Value
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/O
R/W
R/W
0
0
0
0
0
0
0
0