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XRT83VSH314
61
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
TABLE 37: MICROPROCESSOR REGISTER 0X0DH BIT DESCRIPTION
CHANNEL 0-13 (0X0DH-0XDDH)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D[6:0]
6SEG[6:0]
Segment Number Six, Same Description as Register 0x08h
R/W
TABLE 38: MICROPROCESSOR REGISTER 0X0EH BIT DESCRIPTION
CHANNEL 0-13 (0X0EH-0XDEH)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D[6:0]
7SEG[6:0]
Segment Number Seven, Same Description as Register 0x08h
R/W
TABLE 39: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION
CHANNEL 0-13 (0X0FH-0XDFH)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
0
D[6:0]
8SEG[6:0]
Segment Number Eight, Same Description as Register 0x08h
R/W
TABLE 40: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION
GLOBAL REGISTER (0XE0H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
SR/DR
Single Rail/Dual Rail Mode
This bit sets the LIU to receive and transmit digital data in a single
rail or a dual rail format.
0 = Dual Rail Mode
1 = Single Rail Mode
R/W
0
D6
ATAOS
Automatic Transmit All Ones
If ATAOS is selected, an all ones pattern will be transmitted on any
channel that experiences an RLOS condition. If an RLOS condi-
tion does not occur, TAOS will remain inactive.
0 = Disabled
1 = Enabled
R/W
0