參數(shù)資料
型號(hào): XRT83VSH314IB
廠商: Exar Corporation
文件頁(yè)數(shù): 11/80頁(yè)
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 14CH 304TBGA
標(biāo)準(zhǔn)包裝: 27
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 14/14
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 托盤
XRT83VSH314
16
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
2.0
CLOCK SYNTHESIZER
In system design, fewer clocks on the network card could reduce noise and interference. Network cards that
support both T1 and E1 modes must be able to produce 1.544MHz and 2.048MHz transmission data. The
XRT83VSH314 has a built in clock synthesizer that requires only one input clock reference by programming
CLKSEL[3:0] in the appropriate global register. A list of the input clock options is shown in Table 1.
The single input clock reference is used to generate multiple timing references. The first objective of the clock
synthesizer is to generate 1.544MHz and 2.048MHz for each of the 14 channels. This allows each channel to
operate in either T1 or E1 mode independent from the other channels. The state of the equalizer control bits in
the appropriate channel registers determine whether the LIU operates in T1 or E1 mode. The second objective
is to generate additional output clock references for system use. The available output clock references are
shown in Figure 2.
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER
TABLE 1: INPUT CLOCK SOURCE SELECT
CLKSEL[3:0]
INPUT CLOCK REFERENCE
0h (0000)
2.048 MHz
1h (0001)
1.544MHz
8h (1000)
4.096 MHz
9h (1001)
3.088 MHz
Ah (1010)
8.192 MHz
Bh (1011)
6.176 MHz
Ch (1100)
16.384 MHz
Dh (1101)
12.352 MHz
Eh (1110)
2.048 MHz
Fh (1111)
1.544 MHz
Clock
Synthesizer
Internal
Reference
1.544MHz
2.048MHz
Input Clock
8kHz
1.544Mhz
2.048MHz
2.048/4.096/8.192/16.384 MHz
1.544/3.088/6.176/12.352MHz
8kHzOUT
MCLKE1out
MCLKT1out
MCLKT1Nout
MCLKE1Nout
Programmable
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