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參數(shù)資料
| 型號： | XRT83VSH314IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 37/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU SH T1/E1/J1 14CH 304TBGA |
| 標準包裝： | 27 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 14/14 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 托盤 |
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XRT83VSH314
39
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
5.7
Analog Board Continuity Check
This test verifies the per-channel continuity from the Line Side of TIP and RING for both the transmitters and
receivers, through the transformers on the assembly and LIU. Inside the LIU, a MUX and Control logic using
TMS and TCK as reset and clock, successively connect each TIP and RING on the XRT83VSH314 side to two
Analog Test Pins, (ATP_TIP and ATP_RING). Simplified block and timing diagrams are shown in Figure 30
and Figure 31.
5.7.1
Transmitter TTIP and TRING Testing
Testing of each channel must be done in sequence. With a clock signal applied to TCK, Setting TMS to “0” will
begin the test sequence. On the falling edge of the 1st clock pulse after TMS is set to “0”, the sequence will
reset as shown in Figure 31 above. On the 2nd falling clock edge the signal on ATP_TIP and ATP_RING will be
TTIP_0 and TRING_0, respectively. On the falling edge of the 17th clock pulse the signal on ATP_TIP and
ATP_RING wiill be connected to RTIP_0 and RRING_0, respectively. After the 30th clock pulse TMS can be
returned to a “1” and all channels will return to their normal state.
Device side testing is implemented via the ATP_TIP and ATP_RING pins. The Line side Testing is done via the
Line Side Receive and Transmit TIP and RING connections.
Each channel of the device can be tested from the line side by doing the following:
1. Apply a differental 2Vpp, 1MHz signal to the Tx Line Side channel TIP and RING pins.
2. Measure the signal at the device ATP_TIP and ATP_RING pins.
3. If the voltage measured ATP_TTIP/TRING pins is 1Vpp±20%, your assembly is correct.
FIGURE 30. ATP TESTING BLOCK DIAGRAM
FIGURE 31. TIMING DIAGRAM FOR ATP TESTING
XRT83SH314
S
XRT83VSH31
4
1:2
1:1
LINE SIDE Tx
LINE SIDE
Rx
TTIP
TRING
RTIP
RRING
TTIP_n
TRING_n
RRING_n
RTIP_n
MU
X
&
Control Logic
TCK
TMS
ATP_TIP
ATP_RING
n = 0:13
Reset
Tx 0
Tx1
Tx2
4
Rx0
Tx13
3
30
19
18
17
16
15
2
1
RX13
Rx2
Rx1
TCK
TMS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83VSH314IB-F | 功能描述:外圍驅(qū)動器與原件 - PCI 14 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83VSH314IB-SAM | 制造商:Exar Corporation 功能描述:FOR FUJITSU ONLY |
| XRT83VSH316 | 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83VSH316_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83VSH316ES | 功能描述:外圍驅(qū)動器與原件 - PCI 16 CH T1/E1LIUSH LOW COST VERSION RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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