參數(shù)資料
型號: XRT83VSH314IB
廠商: Exar Corporation
文件頁數(shù): 13/80頁
文件大小: 0K
描述: IC LIU SH T1/E1/J1 14CH 304TBGA
標準包裝: 27
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 14/14
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 托盤
XRT83VSH314
17
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
3.0
RECEIVE PATH LINE INTERFACE
The receive path of the XRT83VSH314 LIU consists of 14 independent T1/E1/J1 receivers. The following
section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs.
A
simplified block diagram of the receive path is shown in Figure 3.
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH
3.1
Line Termination (RTIP/RRING)
3.1.1
Internal Termination
The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through
RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU.
This allows one bill of materials for all modes of operation reducing the number of external components
necessary in system design.
The receive termination impedance (along with the transmit impedance) is
selected by programming TERSEL[1:0] to match the line impedance. Selecting the internal impedance is
shown in Table 2.
The XRT83VSH314 has the ability to switch the internal termination to "High" impedance by programming
RxTSEL in the appropriate channel register. For internal termination, set RxTSEL to "1". By default, RxTSEL
is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is also
available to control the receive termination for all channels simultaneously. This hardware pin takes priority
over the register setting if RxTCNTL is set to "1" in the appropriate global register. If RxTCNTL is set to "0", the
state of this pin is ignored. See Figure 4 for a typical connection diagram using the internal termination.
FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION
TABLE 2: SELECTING THE INTERNAL IMPEDANCE
TERSEL[1:0]
RECEIVE TERMINATION
0h (00)
100
1h (01)
110
2h (10)
75
3h (11)
120
HDB3/B8ZS
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak Detector
& Slicer
RTIP
RRING
RCLK
RNEG
RPOS
R
TIP
R
RING
XRT83VSH314 LIU
1:1
Internal Impedance
Line Interface T1/E1/J1
One Bill of Materials
Receiver
Input
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