S
參數(shù)資料
型號(hào)： XRT83SL30IVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 4/76頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 SGL 64TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
XRT83SL30
9
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
JITTER ATTENUATOR
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
JABW
46
I
Jitter Attenuator Bandwidth
In Hardware and E1 mode, when JABW=”0” the jitter attenuator bandwidth
is 10Hz (normal mode). Setting JABW to “1” selects a 1.5Hz Bandwidth for
the Jitter Attenuator and the FIFO length will be automatically set to 64 bits.
In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz, and the
state of this pin has no effect on the Bandwidth. See table under JASEL[1:0]
pin, below.
NOTE: Internally pulled “Low” with a 50k
resistor.
JASEL1
JASEL0
47
48
I
Jitter Attenuator select pin 1
Jitter Attenuator select pin 0
In Hardware Mode, JASEL0, JASEL1 and JABW pins are used to place the
jitter attenuator in the transmit path, the receive path or to disable it and set
the jitter attenuator bandwidth and FIFO size per the following table.
NOTE: These pins are internally pulled "Low" with 50k
resistors.
CLOCK SYNTHESIZER
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
MCLKE1
13
I
E1 Master Clock Input
This input signal is an independent 2.048MHz clock for E1 system with
required accuracy of better than ±50ppm and a duty cycle of 40% to 60%.
MCLKE1 is used in the E1 mode. Its function is to provide internal timing for
the PLL clock recovery circuit, transmit pulse shaping, jitter attenuator block,
reference clock during transmit all ones data and timing reference for the
microprocessor in Host Mode operation.
MCLKE1 is also input to a programmable frequency synthesizer that under
the control of the CLKSEL[2:0] inputs can be used to generate a master
clock from an accurate external source. In systems that have only one mas-
ter clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation.
NOTES:
1.
See pin descriptions for pins CLKSEL[2:0].
2.
Internally pulled “Low” with a 50k
resistor.
Disabled
Transmit
Receive
------
32/32
64/64
------
3
------
10
0
1
0
1
0
1
0
Disabled
Transmit
Receive
--------
32/64
64/64
------
3
------
1.5
0
1
0
1
0
1
JA Path
JA BW (Hz)
FIFO Size
T1/E1
JASEL1
JASEL0
JABW
T1
E1
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