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參數(shù)資料
| 型號： | XRT83SL30IVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 11/76頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 SGL 64TQFP |
| 標準包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應商設備封裝： | 64-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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XRT83SL30
16
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
NLCD
38
O
Network Loop-Code Detection Output pin
This pin operates differently in the Manual or the Automatic Network Loop-
Code detection modes.
In the Manual Loop-Code detection mode (NLCDE1 =”0” and NLCDE0 =”1”,
or NLCDE1 =”1” and NLCDE0 =”0”) this pin gets set to “1” as soon as the
Loop-Up (“00001”) or Loop-Down (“001”) code is detected in the receive data
for longer than 5 seconds. The NLCD pin stays in the “1” state for as long as
the chip detects the presence of the Loop-Code in the receive data and it is
reset to “0” as soon as it stops receiving it.
When the Automatic Loop-Code detection mode (NLCDE1 =”1” and
NLCDE0 =”1”) is initiated, the NLCD output pin is reset to “0” and the chip is
programmed to monitor the receive input data for the Loop-Up Code. The
NLCD pin is set to a “1” to indicate that the Network Loop Code is detected
for more than 5 seconds. Simultaneously the Remote Loop-Back condition is
automatically activated and the chip is programmed to monitor the receive
data for the Network Loop-Down Code. The NLCD pin stays in the “1” state
for as long as the Remote Loop-Back condition is in effect even if the chip
stops receiving the Loop-Up Code. Remote Loop-Back is removed if the chip
detects the “001” pattern for longer than 5 seconds in the receive data.
Detecting the “001” pattern also results in resetting the NLCD output pin.
AISD
39
O
Alarm Indication Signal Detect Output pin
This pin is set to "1" to indicate that an All Ones Signal is detected by the
receiver. The value of this pin is based on the current status of Alarm Indica-
tion Signal detector.
QRPD
40
O
Quasi-random Pattern Detection Output pin
This pin is set to "1" to indicate that the receiver is currently in synchroniza-
tion with the QRSS pattern. The value of this pin is based on the current sta-
tus of Quasi-random pattern detector.
POWER AND GROUND
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
TAGND
7
****
Transmitter Analog Ground
TAVDD
9
****
Transmitter Analog Positive Supply (3.3V + 5%)
RAGND
6
****
Receiver Analog Ground
RAVDD
3
****
Receiver Analog Positive Supply (3.3V± 5%)
VDDPLL
12
****
Analog Positive Supply for Master Clock Synthesizer PLL (3.3V± 5%)
GNDPLL
15
****
Analog Ground for Master Clock Synthesizer PLL
DVDD
36
****
Digital Positive Supply (3.3V± 5%)
AVDD
31
****
Analog Positive Supply (3.3V± 5%)
DGND
37
****
Digital Ground
AGND
32
****
Analog Ground
ALARM FUNCTION/OTHER
SIGNAL NAME
PIN #TYPE
DESCRIPTION
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