參數(shù)資料
型號(hào)： XRT83SL30IVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 1/76頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 SGL 64TQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT83SL30
SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
JUNE 2006
REV. 1.0.1
GENERAL DESCRIPTION
The XRT83SL30 is a fully integrated single-channel
short-haul line interface unit for T1(1.544Mbps) 100
,
E1(2.048Mbps)
75
or 120 and J1 110
applications.
In T1 applications, the XRT83SL30 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements.
The
XRT83SL30
provides
both
Serial
Host
microprocessor interface and Hardware Mode for
programming and control. Both B8ZS and HDB3
encoding and decoding functions are included and
can be disabled as required. On-chip crystal-less jitter
attenuator with a 32 or 64 bit FIFO can be placed
either in the receive or the transmit path with loop
bandwidths of less than 3Hz. The XRT83SL30
provides a variety of loop-back and diagnostic
features as well as transmit driver short circuit
detection and receive loss of signal monitoring. It
supports internal impedance matching for 75
, 100,
110
and 120 for both transmitter and receiver. For
the receiver this is accomplished with internal
resistors or through the combination of one single
fixed value external resistor and programmable
internal resistors. In the absence of the power supply,
the transmit output and receive input are tri-stated
allowing for redundancy applications. The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
FEATURES
(See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL30 T1/E1/J1 LIU (HOST MODE)
HW/HOST
CS
INT
ICT
TPOS / TDATA
TNEG / CODES
TCLK
QRPD
RCLK
RNEG / LCV
RPOS / RDATA
NLCD
RLOS
RTIP
RRING
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO
TTIP
TRING
TXON
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
DRIVE
MONITOR
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
JA
SEL
ECT
NLCD ENABLE
QRSS ENABLE
SDO
SCLK
SDI
RESET
Serial Interface
TEST
TAOS
ENABLE
MCLKE1
MCLKT1
MCLKOUT
AISD
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