REV. 1.0.7 MCLKT1 K1 I T1 Master Clock Input This signal is an independent 1.544" />
參數(shù)資料
型號(hào): XRT83SH38IB-F
廠商: Exar Corporation
文件頁(yè)數(shù): 8/78頁(yè)
文件大小: 0K
描述: IC LIU SH T1/E1/J1 8CH 225BGA
標(biāo)準(zhǔn)包裝: 84
類型: 線路接口裝置(LIU)
驅(qū)動(dòng)器/接收器數(shù): 8/8
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 225-BGA
供應(yīng)商設(shè)備封裝: 225-BGA(19x19)
包裝: 托盤
XRT83SH38
13
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
MCLKT1
K1
I
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with accuracy better
than ±50ppm and duty cycle within 40% to 60%. MCLKT1 is used in the T1 mode.
NOTE: All channels must operate at the same clock rate, either T1, E1 or J1. This
pin is internally pulled "Low" with a 50k
resistor.
MCLKE1
J1
I
E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle of
40% to 60% can be provided at this pin. In systems that have only one master clock
source available (E1 or T1), that clock should be connected to both MCLKE1 and
MCLKT1 inputs for proper operation.
NOTE: All channels of the XRT83SH38 must be operated at the same clock rate,
either T1, E1 or J1. This pin is internally pulled “Low” with a 50k
resistor.
CLKSEL0
CLKSEL1
CLKSEL2
A8
B8
C8
I
Clock Select inputs for Master Clock Synthesizer
Hardware Mode Only
CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be
used to generate a master clock from an external accurate clock source according to
the table below.
MCLKRATE is automatically generated from the state of the
EQC[4:0] pins.
NOTE: These pins are internally pulled “Low” with a 50k
resistor.
SIGNAL NAME
BGA
LEAD #
TYPE
DESCRIPTION
2048
1544
MCLKE1
kHz
8
16
56
8
56
64
128
256
128
2048
1544
M CLKT1
kHz
1544
X
1544
X
2048
1544
2048
CLKOUT/
kHz
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
1
CLKSEL0
0
1
0
1
0
1
0
CLKSEL1
1
0
1
0
1
0
CLKSEL2
0
1
0
1
0
1
0
1544
2048
X
2048
1544
0
1
0
1
M CLKRATE
1
0
1
0
1
0
1
0
1
0
1
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