REV. 1.0.7 data can be updated on either edge of RCLK. By default, data is updat" />
參數(shù)資料
型號(hào)： XRT83SH38IB-F
廠商： Exar Corporation
文件頁數(shù)： 19/78頁
文件大小： 0K
描述： IC LIU SH T1/E1/J1 8CH 225BGA
標(biāo)準(zhǔn)包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT83SH38
23
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To
update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 8 is a
timing diagram of the receive data updated on the rising edge of RCLK. Figure 9 is a timing diagram of the
receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 5.
FIGURE 8. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK
FIGURE 9. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK
NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified
3.2.1
Receive Sensitivity
To meet short haul requirements, the XRT83SH38 can accept T1/E1/J1 signals that have been attenuated by
12dB of flat loss in E1 mode or by 655 feet of cable loss along with 6dB of flat loss in T1 mode. However, the
XRT83SH38 can tolerate cable loss and flat loss beyond the industry specifications. The receive sensitivity in
the short haul mode is approximately 4,000 feet without experiencing bit errors, LOF, pattern synchronization,
etc. Although data integrity is maintained, the RLOS function (if enabled) will report an RLOS condition
TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
RCLK Duty Cycle
RCDU
45
50
55
%
Receive Data Setup Time
RSU
150
-
ns
Receive Data Hold Time
RHO
150
-
ns
RCLK to Data Delay
RDY
-
40
ns
RCLK Rise Time (10% to 90%)
with 25pF Loading
RCLKR
-
40
ns
RCLK Fall Time (90% to 10%)
with 25pF Loading
RCLKF
-
40
ns
RCLK
RP O S
or
RNE G
R
DY
RCLK
R
RCLK
F
R
OH
RCLK
RPOS
or
RNEG
R
DY
RCLK
F
RCLK
R
OH
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