REV. 1.0.7 D1 RLOS Receiver Loss of Signal The receiver loss of signal detection" />
參數(shù)資料
型號： XRT83SH38IB-F
廠商： Exar Corporation
文件頁數(shù)： 59/78頁
文件大?。?/td> 0K
描述： IC LIU SH T1/E1/J1 8CH 225BGA
標準包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT83SH38
59
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
D1
RLOS
Receiver Loss of Signal
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0x80h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
D0
QRPD
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0x80h.
0 = No Alarm
1 = A QRP is detected
RO
0
TABLE 29: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION
CHANNEL 0-7 (0X06H-0X76H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used.
D6
DMOIS
Digital Monitor Output Status
0 = No change
1 = Change in status occurred
RUR
0
D5
FLSIS
FIFO Limit Status
0 = No change
1 = Change in status occurred
RUR
0
D4
LCV/OFIS Line Code Violation / Overflow Status
0 = No change
1 = Change in status occurred
RUR
0
D3
Reserved
This Register Bit is Not Used.
D2
AISDIS
Alarm Indication Signal Status
0 = No change
1 = Change in status occurred
RUR
0
NOTE: The GIE bit in the global register 0x80h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 28: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CHANNEL 0-7 (0X05H-0X75H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
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