REV. 1.0.7 PIN DESCRIPTION BY FUNCTION RECEIVE SECTION S<" />
參數(shù)資料
型號(hào)： XRT83SH38IB-F
廠商： Exar Corporation
文件頁數(shù)： 77/78頁
文件大?。?/td> 0K
描述： IC LIU SH T1/E1/J1 8CH 225BGA
標(biāo)準(zhǔn)包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT83SH38
5
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
PIN DESCRIPTION BY FUNCTION
RECEIVE SECTION
SIGNAL NAME
BGA
LEAD #
TYPE
DESCRIPTION
RXON
K16
I
Receiver On
Hardware Mode Only
This pin is used to enable the receivers for all channels. By default, the receivers
are turned on in hardware mode. To turn the receivers off, this "Low".
NOTE: Internally pulled "High" with 50k
resistor.
RLOS0
RLOS1
RLOS2
RLOS3
RLOS4
RLOS5
RLOS6
RLOS7
C3
H4
H15
A16
V3
L2
J15
T15
O
Receive Loss of Signal
When a receive loss of signal occurs according to ITU-T G.775, the RLOS pin will go
"High" for a minimum of one RCLK cycle. RLOS will remain "High" until the loss of
signal condition clears. See the Receive Loss of Signal section of this datasheet for
more details.
NOTE: This pin can be used for redundancy applications to initiate an automatic
switch to a backup card.
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
B3
H3
H16
A17
U3
L3
M15
U16
O
Receive Clock Output
RCLK is the recovered clock from the incoming data stream. If the incoming signal
is absent or RTIP/RRING are in "High-Z", RCLK maintains its timing by using an
internal master clock as its reference. RPOS/RNEG data can be updated on either
edge of RCLK selected by RCLKE.
NOTE: RCLKE is a global setting that applies to all 8 channels.
RNEG/LCV0
RNEG/LCV1
RNEG/LCV2
RNEG/LCV3
RNEG/LCV4
RNEG/LCV5
RNEG/LCV6
RNEG/LCV7
A2
H2
H18
B16
T4
M4
M16
V17
O
RNEG/LCV_OF Output
In dual rail mode, this pin is the receive negative data output. In single rail mode,
this pin is a Line Code Violation / Counter Overflow indicator. If LCV is selected by
programming the appropriate global register and if a line code violation, a bi-polar
violation, or excessive zeros occur, the LCV pin will pull "High" for a minimum of one
RCLK cycle. LCV will remain "High" until there are no more violations. However, if
OF (Overflow) is selected the LCV pin will pull "High" if the internal LCV counter is
saturated. The LCV pin will remain "High" until the LCV counter is reset.
RPOS0
RPOS1
RPOS2
RPOS3
RPOS4
RPOS5
RPOS6
RPOS7
B2
G2
D15
B17
U2
M3
L17
T17
O
RPOS/RDATA Output
Receive digital output pin. In dual rail mode, this pin is the receive positive data out-
put. In single rail mode, this pin is the receive non-return to zero (NRZ) data output.
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