參數(shù)資料
型號(hào)： XRT83L314IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA304
封裝： TBGA-304
文件頁(yè)數(shù)： 74/84頁(yè)
文件大?。?/td> 631K
代理商： XRT83L314IB
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
CLOCK SELECT REGISTER
70
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits in
register 0xE9h. Therefore, if the clock selection bits are being programmed, the frequency of the PLL output
will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within
the same register while selecting the input/output clock frequency. For best results, register 0xE9h can be
broken down into two sub-registers with the MSB being bits D[7:4] and the LSB being bits D[3:0] as shown in
Figure 45. Note: Bits D[7:6] are reserved.
F
IGURE
45. R
EGISTER
0
X
E9
H
S
UB
R
EGISTERS
Programming Examples:
Example 1: Changing bits D[7:4]
If bits D[7:4] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[3:0]
If bits D[3:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection (LSB) and then change bits D[5:4] (MSB) on the SECOND write, or vice-
versa. No order or sequence is necessary.
T
ABLE
50: M
ICROPROCESSOR
R
EGISTER
0
X
E9
H
B
IT
D
ESCRIPTION
G
LOBAL
R
EGISTER
(0
X
E9
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
R/W
0
D6
Reserved
This Register Bit is Not Used
R/W
0
D0
D1
D2
D3
D4
D5
D6
D7
MSB
LSB
Clock Selection Bits
ALLT1/E1, CLKCNTL
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