參數(shù)資料
型號: XRT83L314IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA304
封裝: TBGA-304
文件頁數(shù): 72/84頁
文件大?。?/td> 631K
代理商: XRT83L314IB
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
68
T
ABLE
47: M
ICROPROCESSOR
R
EGISTER
0
X
E6
H
B
IT
D
ESCRIPTION
G
LOBAL
R
EGISTER
(0
X
E6
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
R/W
0
D6
Reserved
This Register Bit is Not Used
R/W
0
D5
Reserved
This Register Bit is Not Used
R/W
0
D4
allRST
LCV Counter Reset for All Channels
This bit is used to reset all internal LCV counters to their default
state 0000h. This bit must be set to "1" for 1
μ
S.
0 = Normal Operation
1 = Resets All Counters
R/W
0
D3
allUPDATE
LCV Counter Update for All Channels
This bit is used to latch the contents of all 14 counters into holding
registers so that the value of each counter can be read. The chan-
nel is addressed by using bits D[3:0] in register 0xE5h.
0 = Normal Operation
1 = Updates All Channels
R/W
0
D2
BYTEsel
LCV Counter Byte Select
This bit is used to select the MSB or LSB for Reading the contents
of the LCV counter for a given channel. The channel is addressed
by using bits D[3:0] in register 0xE5h. By default, the LSB byte is
selected.
0 = Low Byte
1 = High Byte
R/W
0
D1
chUPDATE
LCV Counter Update Per Channel
This bit is used to latch the contents of the counter for a given
channel into a holding register so that the value of the counter can
be read. The channel is addressed by using bits D[3:0] in register
0xE5h.
0 = Normal Operation
1 = Updates the Selected Channel
R/W
0
D0
chRST
LCV Counter Reset Per Channel
This bit is used to reset the LCV counter of a given channel to its
default state 0000h. The channel is addressed by using bits D[3:0]
in register 0xE5h. This bit must be set to "1" for 1
μ
S.
0 = Normal Operation
1 = Resets the Selected Channel
R/W
0
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