參數(shù)資料
型號： XRT83L314IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA304
封裝： TBGA-304
文件頁數(shù)： 4/84頁
文件大?。?/td> 631K
代理商： XRT83L314IB
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
TABLE OF CONTENTS
I
GENERAL DESCRIPTION.............................................................................................................. 1
APPLICATIONS ..........................................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
THE
XRT83L314.................................................................................................................................... 1
FEATURES
.....................................................................................................................................................................2
PRODUCT ORDERING INFORMATION..................................................................................................2
PIN OUT OF THE XRT83L314........................................................................................................ 3
T
ABLE
OF
C
ONTENTS
............................................................................................................I
PIN DESCRIPTIONS....................................................................................................................... 3
M
ICROPROCESSOR
........................................................................................................................................................3
R
ECEIVER
S
ECTION
.......................................................................................................................................................4
T
RANSMITTER
S
ECTION
..................................................................................................................................................7
C
ONTROL
F
UNCTION
......................................................................................................................................................9
C
LOCK
S
ECTION
............................................................................................................................................................9
P
OWER
AND
G
ROUND
..................................................................................................................................................10
N
O
C
ONNECTS
............................................................................................................................................................12
1.0 CLOCK SYNTHESIZER .......................................................................................................................13
T
ABLE
1: I
NPUT
C
LOCK
S
OURCE
S
ELECT
.............................................................................................................................................. 13
F
IGURE
2. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
C
LOCK
S
YNTHESIZER
................................................................................................... 14
1.1 ALL T1/E1 MODE ........................................................................................................................................... 14
2.0 RECEIVE PATH LINE INTERFACE .....................................................................................................14
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
............................................................................................................ 14
2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 15
2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 15
F
IGURE
4. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
.......................................................................................... 15
T
ABLE
2: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
.................................................................................................................................... 15
2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES..................... 16
F
IGURE
5. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
O
NE
E
XTERNAL
F
IXED
R
ESISTOR
.............................................................................. 16
T
ABLE
3: S
ELECTING
THE
V
ALUE
OF
THE
E
XTERNAL
F
IXED
R
ESISTOR
.................................................................................................... 16
2.2 EQUALIZER CONTROL ................................................................................................................................. 17
F
IGURE
6. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
E
QUALIZER
AND
P
EAK
D
ETECTOR
................................................................................. 17
2.3 CABLE LOSS INDICATOR ............................................................................................................................. 17
F
IGURE
7. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
C
ABLE
L
OSS
I
NDICATOR
................................................................................................ 17
2.4 EQUALIZER ATTENUATION FLAG .............................................................................................................. 18
F
IGURE
8. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
E
QUALIZER
A
TTENUATION
F
LAG
.................................................................................... 18
2.5 PEAK DETECTOR AND SLICER ................................................................................................................... 18
T
ABLE
4: S
ELECTING
THE
S
LICER
L
EVEL
FOR
THE
P
EAK
D
ETECTOR
....................................................................................................... 18
2.6 CLOCK AND DATA RECOVERY ................................................................................................................... 19
F
IGURE
9. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK..................................................................................................... 19
F
IGURE
10. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK................................................................................................. 19
2.6.1 RECEIVE SENSITIVITY .............................................................................................................................................. 20
F
IGURE
11. T
EST
C
ONFIGURATION
FOR
M
EASURING
R
ECEIVE
S
ENSITIVITY
............................................................................................ 20
T
ABLE
5: T
IMING
S
PECIFICATIONS
FOR
RCLK/RPOS/RNEG................................................................................................................. 20
2.6.2 INTERFERENCE MARGIN ......................................................................................................................................... 21
F
IGURE
12. T
EST
C
ONFIGURATION
FOR
M
EASURING
I
NTERFERENCE
M
ARGIN
......................................................................................... 21
2.6.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 21
F
IGURE
13. I
NTERRUPT
G
ENERATION
P
ROCESS
B
LOCK
......................................................................................................................... 21
2.6.3.1 RLOS (R
ECEIVER
L
OSS
OF
S
IGNAL
) ..................................................................................................................... 21
F
IGURE
14. A
NALOG
R
ECEIVE
L
OS
OF
S
IGNAL
FOR
T1/E1/J1................................................................................................................ 22
2.6.3.2 EXLOS (E
XTENDED
L
OSS
OF
S
IGNAL
) .................................................................................................................. 22
2.6.3.3 AIS (A
LARM
I
NDICATION
S
IGNAL
) ......................................................................................................................... 22
2.6.3.4 NLCD (N
ETWORK
L
OOP
C
ODE
D
ETECTION
) .......................................................................................................... 22
T
ABLE
6: A
NALOG
RLOS D
ECLARE
/C
LEAR
(T
YPICAL
V
ALUES
)
FOR
T1/E1............................................................................................. 22
F
IGURE
15. P
ROCESS
B
LOCK
FOR
A
UTOMATIC
L
OOP
C
ODE
D
ETECTION
................................................................................................ 23
2.6.3.5 FLSD (FIFO L
IMIT
S
TATUS
D
ETECTION
) ............................................................................................................... 24
2.6.3.6 LCV/OFD (L
INE
C
ODE
V
IOLATION
/ C
OUNTER
O
VERFLOW
D
ETECTION
) ................................................................. 24
2.7 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24
2.8 HDB3/B8ZS DECODER .................................................................................................................................. 24
2.9 RPOS/RNEG/RCLK ........................................................................................................................................ 25
F
IGURE
16. S
INGLE
R
AIL
M
ODE
W
ITH
A
F
IXED
R
EPEATING
"0011" P
ATTERN
......................................................................................... 25
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