參數(shù)資料
型號(hào)： XRT83L314IB
廠(chǎng)商： EXAR CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA304
封裝： TBGA-304
文件頁(yè)數(shù)： 63/84頁(yè)
文件大?。?/td> 631K
代理商： XRT83L314IB
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
N
OTE
:
The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
T
ABLE
30: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
REV. 1.0.0
59
D2
AISD
Alarm Indication Signal
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0x04h and GIE is set to "1" in the global regis-
ter 0xE0h.
0 = No Alarm
1 = An all ones signal is detected
RO
0
D1
RLOS
Receiver Loss of Signal
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
D0
QRPD
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0xE0h.
0 = No Alarm
1 = A QRP is detected
RO
0
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
0
X
06
H
B
IT
D
ESCRIPTION
C
HANNEL
0-13 (0
X
06
H
-0
X
D6
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
EQFLAGS
Equalizer Attenuation Flag Status
0 = No change
1 = Change in status occurred
RUR
0
D6
DMOIS
Digital Monitor Output Status
0 = No change
1 = Change in status occurred
RUR
0
D5
FLSIS
FIFO Limit Status
0 = No change
1 = Change in status occurred
RUR
0
C
HANNEL
0-13 (0
X
05
H
-0
X
D5
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
相關(guān)PDF資料
PDF描述
XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83L34IV QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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XRT83SH314IB 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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