參數(shù)資料
型號(hào): XRT83L314IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA304
封裝: TBGA-304
文件頁數(shù): 69/84頁
文件大?。?/td> 631K
代理商: XRT83L314IB
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
65
T
ABLE
43: M
ICROPROCESSOR
R
EGISTER
0
X
E2
H
B
IT
D
ESCRIPTION
T
ABLE
44: M
ICROPROCESSOR
R
EGISTER
0
X
E3
H
B
IT
D
ESCRIPTION
D1
EXLOS
Extended Loss of Zeros
The number of zeros required to declare a Digital Loss of Signal is
extended to 4,096.
0 = Normal Operation
1 = Enables the EXLOS function
R/W
0
D0
ICT
In Circuit Testing
0 = Normal Operation
1 = Sets all output pins to "High" impedance for in circuit testing
R/W
0
G
LOBAL
R
EGISTER
(0
X
E2
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
R/W
0
D6
RxTCNTL
Receive Termination Select Control
This bit sets the LIU to control the RxTSEL function with either the
individual channel register bit or the global hardware pin.
0 = Control of the receive termination is set to the register bits
1 = Control of the receive termination is set to the hardware pin
R/W
0
D5
D4
D3
D2
D1
D0
EQFLAG5
EQFLAG4
EQFLAG3
EQFLAG2
EQFLAG1
EQFLAG0
Equalizer Attenuation Flag
EQFLAG[5:0] is used to generate an interrupt condition for an
RLOS other than the default setting described in the datasheet. A
desired value can be programmed into this register. If EQFLAGE
is enabled in register 0x04h and if this 6-Bit binary word is equal to
the 6-Bit cable loss indicator, an interrupt will be generated.
R/W
0
0
0
0
0
0
G
LOBAL
R
EGISTER
(0
X
E3
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
R/W
0
D6
Reserved
This Register Bit is Not Used
R/W
0
D5
Reserved
This Register Bit is Not Used
R/W
0
D4
Reserved
This Register Bit is Not Used
R/W
0
G
LOBAL
R
EGISTER
(0
X
E1
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
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