參數(shù)資料
型號(hào): XRT83L314IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA304
封裝: TBGA-304
文件頁(yè)數(shù): 18/84頁(yè)
文件大?。?/td> 631K
代理商: XRT83L314IB
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
14
F
IGURE
2. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
C
LOCK
S
YNTHESIZER
1.1
To reduce system noise and power consumption, the XRT83L314 offers an ALL T1/E1 mode. Since most line
card designs are configured to operate in T1 or E1 only, the LIU can be selected to shut off the timing
references for the mode not being used by programming the appropriate global register. By default the ALL
T1/E1 mode is enabled (ALLT1/E1 bit = "0"). If the LIU is configured for T1, all E1 clock references and the
8kHz reference are shut off internally to the chip. This reduces the amount of internal clocks switching within
the LIU, hence reducing noise and power consumption. In E1 mode, the T1 clock references are internally
shut off, however the 8kHz reference is available. To disable this feature, the ALLT1/E1 bit must be set to a "1"
in the appropriate global register.
ALL T1/E1 Mode
2.0
RECEIVE PATH LINE INTERFACE
The receive path of the XRT83L314 LIU consists of 14 independent T1/E1/J1 receivers. The following section
describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified
block diagram of the receive path is shown in Figure 3.
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
Clock
Synthesizer
Internal
Reference
1.544MHz
2.048MHz
Input Clock
8kHz
1.544Mhz
2.048MHz
2.048/4.096/8.192/16.384 MHz
1.544/3.088/6.176/12.352MHz
8kHzOUT
MCLKE1out
MCLKT1out
MCLKT1Nout
MCLKE1Nout
Programmable
Programmable
HDB3/B8ZS
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak Detector
& Slicer
Rx Equalizer
Rx Equalizer
Control
RTIP
RRING
RCLK
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