參數(shù)資料
型號: XRT83L30IV-F
廠商: Exar Corporation
文件頁數(shù): 8/78頁
文件大?。?/td> 0K
描述: IC LIU LH/SH T1/E1 SGL 64TQFP
標(biāo)準(zhǔn)包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: T1,E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 1016-1633
XRT83L30IV-F-ND
XRT83L30
13
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
CONTROL FUNCTION
RESET
41
I
Hardware Reset (Active "Low")
When this pin is tied “Low” for more than 10s, the device is put in the reset
state.
Pulling RESET “Low” while the ICT pin is also “Low” will put the chip in fac-
tory test mode. This condition should never happen during normal operation.
NOTE: Internally pulled “High” with a 50k
resistor.
SR/DR
28
I
Single-Rail/Dual-Rail Data Format
In Hardware mode, connect this pin "Low" to select transmit and receive
data format in dual-rail mode. In this mode, HDB3 or B8ZS encoder and
decoder are not available.
Connect this pin "High" to select single-rail data format.
NOTE: Internally pulled "Low" with a 50k
resistor.
LOOP1
LOOP0
29
30
I
Loop-back Control pin 1
Loop-back Control pin 0
In Hardware mode, LOOP[1:0] pins are used to control the Loop-back func-
tions according to the following table:
NOTE: Internally pulled "Low" with a 50k
resistor.
EQC4
SDI
21
I
Equalizer Control Input pin 4
In Hardware mode, this pin together with EQC[3:0] are used for controlling
the transmit pulse shaping, transmit line build-out (LBO), receive monitoring
and also to select T1, E1 or J1 modes of operation. See
Table 5 for descrip-
tion of Transmit Equalizer Control bits.
Serial Data Input
EQC3
SDO
22
I
O
Equalizer Control Input pin 3
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Data Output
EQC2
SCLK
23
I
Equalizer Control Input pin 2
See EQC4/SDI description for further explanation for the usage of this pin.
Serial Interface Clock Input
LOOP1
LOOP0
0
1
0
1
MODE
Normal Mode
Local Loop-Back
Remote Loop-Bac
Digital Loop-Back
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