參數(shù)資料
型號： XRT83L314IB-L
廠商： Exar Corporation
文件頁數(shù)： 1/84頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 14CH 304TBGA
標(biāo)準(zhǔn)包裝： 27
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 14/14
規(guī)程： T1，E1，J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 304-LBGA
供應(yīng)商設(shè)備封裝： 304-TBGA（31x31）
包裝： 托盤
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
MAY 2004
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83L314 is a fully integrated 14-channel long-
haul and short-haul line interface unit (LIU) that
operates from a single 3.3V power supply.
Using
internal termination, the LIU provides one bill of
materials to operate in T1, E1, or J1 mode
independently on a per channel basis with minimum
external
components.
The
LIU
features
are
programmed through a standard microprocessor
interface. EXAR’s LIU has patented high impedance
circuits that allow the transmitter outputs and receiver
inputs to be high impedance when experiencing a
power failure or when the LIU is powered off. Key
design features within the LIU optimize 1:1 or 1+1
redundancy and non-intrusive monitoring applications
to ensure reliability without using relays.
The on-chip clock synthesizer generates T1/E1/J1
clock rates from a selectable external clock frequency
and has five output clock references that can be used
for external timing (8kHz, 1.544Mhz, 2.048Mhz,
nxT1/J1, nxE1).
Additional features include RLOS, a 16-bit LCV
counter for each channel, AIS, QRSS generation/
detection, Network Loop Code generation/detection,
TAOS, DMO, and diagnostic loopback modes.
APPLICATIONS
T1 Digital Cross Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public Switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Integrated Multi-Service Access Platforms (IMAPs)
Integrated Access Devices (IADs)
Inverse Multiplexing for ATM (IMA)
Wireless Base Stations
FIGURE 1. BLOCK DIAGRAM OF THE XRT83L314
HDB3/B8ZS
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse
Shaper &
Pattern Gen
HDB3/B8ZS
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak
Detector
& Slicer
Rx
Equalizer
NLCD
Detection
NLCD
Generation
QRSS
Generation
& Detection
Rx Equalizer
Control
AIS & LOS
Detector
Driver
Monitor
1 of 14 Channels
Test
Microprocessor
Interface
Programmable Master
Clock Synthesizer
Line
Driver
Remote
Loopback
Digital
Loopback
Analog
Loopback
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
[7
:0
]
[10:
0]
A
DDR
DA
T
A
AL
E
u
P
CLK
M
CLK
in
8kHzOUT
MCLKE1out
MCLKT1out
MCLKE1Nout
MCLKT1Nout
RTIP
RRING
TRING
TTIP
TxON
RxON
ICT
Res
et
u
PT
S2
u
PT
S1
RxTSEL
TEST
u
PT
S0
DMO
RLOS
IN
T
CS
RDY
_T
A
RD_W
E
W
R_R/
W
C
S
[5
:1
]
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