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XRT83L30
62
REV. 1.0.1
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
TABLE 35: MICROPROCESSOR REGISTER #17 BIT DESCRIPTION
REGISTER ADDRESS
10001
NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
D7
Reserved
R/W
0
D6
CLKSEL2
Clock Select Inputs for Master Clock Synthesizer bit 2
: In
Host
mode, CLKSEL[2:0] are input signals to a programmable
frequency synthesizer that can be used to generate a master
clock from an external accurate clock source according to the fol-
lowing table:
In Hardware mode the state of these bits are ignored and the
master frequency PLL is controlled by the corresponding Hard-
ware
pins.
R/W
0
D5
CLKSEL1
Clock Select inputs for Master Clock Synthesizer bit 1:
See
description of bit D6 for function of this bit.
R/W
0
D4
CLKSEL0
Clock Select inputs for Master Clock Synthesizer bit 0:
See
description of bit D6 for function of this bit.
R/W
0
2048
1544
MCLKE1
kHz
8
16
56
8
56
64
128
256
128
2048
1544
M CLKT1
kHz
1544
X
1544
X
2048
1544
2048
CLKOUT
kHz
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
0
1
CLKSEL0
0
1
0
1
0
1
0
CLKSEL1
1
0
1
0
1
0
CLKSEL2
0
1
0
1
0
1
0
1544
2048
X
2048
1544
0
1
0
1
MCLKRATE
1
0
1
0
1
0
1
0
1
0
1