參數(shù)資料
型號: XRT83L30IV-F
廠商: Exar Corporation
文件頁數(shù): 17/78頁
文件大?。?/td> 0K
描述: IC LIU LH/SH T1/E1 SGL 64TQFP
標準包裝: 160
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: T1,E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 1016-1633
XRT83L30IV-F-ND
XRT83L30
21
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
cable loss (frequency), not flat loss (resistive). Once the E1 input signal has been normalized to 0dB by adding
the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB.
The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so
that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable
attenuation of -49dB. See Figure 9 for a simplified diagram.
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes by controlling the TNEG/CODE pin or
the CODE interface bit. The decoder function is only active in single-rail Mode. When selected, receive data in
this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1 systems. Bipolar violations that do
not conform to the coding scheme will be reported as Line Code Violation at the RNEG/LCV pin. The length of
the LCV pulse is one RCLK cycle for each code violation. Excessive number of zeros in the receive data
stream is also reported as an error at the same output pin. If AMI decoding is selected in single rail mode,
every bipolar violation in the receive data stream will be reported as an error at the RNEG/LCV pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes. In Host mode, the sampling edge of RCLK output
can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE interface bit, receive
data output at RPOS/RDATA and RNEG/LCV are updated on the falling edge of RCLK. Writing a “0” to the
RCLKE register, updates the receive data on the rising edge of RCLK. In Hardware mode the same feature is
available under the control of the RCLKE pin.
FIGURE 9. SIMPLIFIED DIAGRAM OF EXTENDED RLOS MODE (E1 ONLY)
FIGURE 10. RECEIVE CLOCK AND OUTPUT DATA TIMING
Norm alized up to +45dB Max
Declare LOS
Clear LOS
-9dB
+3dB
Clear LOS
Declare LOS
+3dB
-9dB
RCLK
R
RCLK
F
RCLK
RPOS
or
RNEG
R
DY
R
HO
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