參數(shù)資料
型號(hào)： XRT83L30IV-F
廠商： Exar Corporation
文件頁數(shù)： 19/78頁
文件大小： 0K
描述： IC LIU LH/SH T1/E1 SGL 64TQFP
標(biāo)準(zhǔn)包裝： 160
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： T1，E1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤
其它名稱： 1016-1633
XRT83L30IV-F-ND
XRT83L30
23
SINGLE-CHANNEL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.1
ARBITRARY PULSE GENERATOR
In T1 mode only, the arbitrary pulse generator divides the pulse into eight individual segments. Each segment
is set by a 7-Bit binary word by programming the appropriate register. This allows the system designer to set
the overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit
is set to “1”, the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is
set to “0”, the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in Figure 11.
NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter output will result in an all zero pattern
to the line.
TRANSMITTER
DIGITAL DATA FORMAT
Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature is
available under both Hardware and Host control modes. The dual or single-rail data format is determined by
the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host mode. In single-rail mode,
transmit clock and NRZ data are applied to TCLK and TPOS/TDATA pins respectively. In single-rail and
Hardware mode the TNEG/CODE input can be used as the CODES function. With TNEG/CODE tied “Low”,
HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes respectively. With TNEG/CODE tied
“High”, the AMI coding scheme is selected. In both dual or single-rail modes of operations, the transmitter
converts digital input data to a bipolar format before being transmitted to the line.
TRANSMIT CLOCK (TCLK) SAMPLING EDGE
Serial transmit data at TPOS/TDATA and TNEG/CODE are clocked into the XRT83L30 under the
synchronization of TCLK. With a “0” written to the TCLKE interface bit, or by pulling the TCLKE pin “Low”, input
data is sampled on the falling edge of TCLK. The sampling edge is inverted with a “1” written to TCLKE
interface bit, or by connecting the TCLKE pin “High”.
FIGURE 11. ARBITRARY PULSE SEGMENT ASSIGNMENT
1
2
3
4
5
6
7
8
Segment
Register
1
0xn8
2
0xn9
3
0xna
4
0xnb
5
0xnc
6
0xnd
7
0xne
8
0xnf
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