參數(shù)資料
型號(hào)： XRT82L24AIV-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 39/39頁(yè)
文件大小： 0K
描述： IC LIU E1 QAUD 100TQFP
標(biāo)準(zhǔn)包裝： 90
類(lèi)型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： E1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤(pán)
其它名稱： XRT82L24AIV-F-ND
á
XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
7
18
RDY_DTACK
O
Ready Output (Data Transfer Acknowledge Output).
With Intel bus timing, RDY is asserted "High" to indicate the device has com-
pleted a read or write operation. When configured in Motorola bus timing,
DTACK is asserted Low to indicate the device has completed a read or write
cycle.
67
68
69
70
A[3]
A[2]
A[1]
A[0]
I
Host Mode, Microprocessor Interface Address Bus [3]
Host Mode, Microprocessor Interface Address Bus [2]
Host Mode, Microprocessor Interface Address Bus [1]
Host Mode, Microprocessor Interface Address Bus [0].
56
57
58
59
60
61
62
63
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
I/O
Data Bus[7:0].
Microprocessor read/write data bus pins.
CLOCKS
66
MCLK
I
Master Clock Input.
This signal is an independent 2.048MHz clock with accuracy better than
±50ppm and duty cycle within 40% to 60%. The function of MCLK is to provide
internal timing for the PLL clock recovery circuit, jitter attenuator block, refer-
ence clock during transmit all ones data and timing reference for the micropro-
cessor in Host Mode operation.
If MClk is absent, all receive channels perform as analog front-end (AFE). The
OR-ed RZ data is also available at RxClk output in this mode, instead. The
clock recovery function is disabled.
JITTER ATTENUATOR
56
TXJA
I
Transmit Jitter Attenuator Select.
In Hardware Mode, connect this pin “High” to select jitter attenuator in the trans-
mit path and connect Low to disable jitter attenuator.
Setting RXJA simultaneously "High" also disables jitter attenuator selection.
57
RXJA
I
Receive Jitter Attenuator Select.
In Hardware Mode, connect this pin “High” to select jitter attenuator in the
receive path and connect Low to disable jitter attenuator.
Setting TXJA simultaneously "High" also disables jitter attenuator selection.
CONTROL
8
SR/DR
I
Single rail/Dual Rail Control:
Hardware Mode
Connect this pin “Low” to select transmit and receive data format in dual-rail
mode. In this mode, HDB3 encoder and decoder are not available. Connect this
pin "High" to select single-rail data format.
NOTE: Internally pulled -down with a 50k
resistor.
10
Codes
I
Coding/Decoding Select.
In Hardware Mode, if single-rail data format is selected (pin 8 =”1”), connect
this pin "High" to select AMI encoding and decoding. Connect this pin Low to
select HDB3.
PIN DESCRIPTIONS
PIN #NAME
TYPE
DESCRIPTION
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