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參數(shù)資料
| 型號(hào)： | XRT82L24AIV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 22/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1 QAUD 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | E1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | XRT82L24AIV-F-ND |
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
27
TABLE 12: CHANNEL STATUS REGISTER
CHANNEL STATUS REGISTER
PARALLEL PORT ADDRESS CHANNEL 0: 0010
PARALLEL PORT ADDRESS CHANNEL 1: 0101
PARALLEL PORT ADDRESS CHANNEL 2: 1000
PARALLEL PORT ADDRESS CHANNEL 3: 1011
BIT NO.SYMBOL
FUNCTION
REGISTER
TYPE
RESET
VALUE
7DMOn
Driver Monitor Output:
This bit is set to a "1" to indicate current DMO is detected. Any change in the
state of this bit causes an interrupt to be generated. Reading this register bit
does not clear the DMO bit.
R0
6LOSn
Loss of Signal:
This bit is set to a "1" to indicate current LOS condition is detected. Any
change in the state of this bit causes an interrupt to be generated. Reading
this register bit does not clear the LOS bit.
R0
5
LCVn
Line Code Violation:
This bit is set to a "1" to indicate current LCV condition is detected. Any
change in the state of this bit causes an interrupt to be generated. Reading
this register bit does not clear the LCV bit.
R0
4TCKLn
Transmit Clock Loss:
This bit is set to a "1" to indicate current TxClk clock loss is detected. Any
change in the state of this bit causes an interrupt to be generated. Reading
this register bit does not clear the TCKL bit.
R0
3DMOnIS Driver Monitor Output:
This bit is set to a "1" every time the state of DMO status changes since last
read. This bit is cleared by a read operation.
RUR
0
2LOSnIS
Latched- Loss of signal:
This bit is set to a "1" every time the state of LOS changes since last read.
This bit is cleared by a read operation.
RUR
0
1LCVnIS
Latched- Line Code Violation:
This bit is set to a "1" every time the state of LCV changes since last read.
This bit is cleared by a read operation.
RUR
0
0TCLKnIS Latched-Transmit Clock Loss.
This bit is set to a "1" every time the state of TCKL changes since last read.
This bit is cleared by a read operation.
RUR
0
NOTE: n = channel number 0 to 3.
NOTE: Register Type Abrbreviation:
R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
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