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參數(shù)資料
| 型號(hào)： | XRT82L24AIV-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 20/39頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU E1 QAUD 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | E1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | XRT82L24AIV-F-ND |
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XRT82L24A
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.1.2
25
TABLE 10: COMMAND CONTROL REGISTER 0
COMMAND CONTROL REGISTER 0
PARALLEL PORT ADDRESS: 0000
BIT NO.NAME
FUNCTION
REGISTER
TYPE
RESET
VALUE
7
SR/DR
Single/Dual Rail:
Writing a "1" to this bit selects transmit and receive data format in
single-rail mode. In this mode, HDB3/B8ZS/AMI encoder and
decoder are available.
Writing a "0" selects dual-rail mode.
R/W
0
6RZData
RZ Data:
Writing a “1” to this bit selects receive data to pass to the output
after the slicers without re-timing. In this mode, PLL clock recov-
ery, jitter attenuator, decoder and remote loop-back functions are
disabled.
R/W
0
5RCLKE
RxClk Clock Edge:
Writing a "1" to this bit selects receive output data to be updated
on positive edge of RxClk.
Writing a "0" to this bit selects the negative edge of RxClk.
R/W
0
4TCLKE
TxClk Clock Edge:
Writing a "1" to this bit selects positive edge of TxClk to sample
input data.
Write "0" to select negative edge.
R/W
0
3DATAP
DATA Polarity:
Writing a "0" to this bit selects transmit input and receive output
data to be active-high.
Write "1" to select active-low.
R/W
0
2CODES
Coding/Decoding Select:
This bit is used in conjunction with SR/DR bit 1. If SR/DR is "1",
writing a "0" to this bit selects HDB3 coding. Writing a "1" to this
bit position selects AMI code.
R/W
0
1GIE
Global Interrupt Enable:
Writing a "0" to this bit globally disables interrupt generation
caused by any alarm generated within the line interface. Write a
"1" to enable interrupt generation.
R/W
0
SRESET
Software Reset:
Writing a "1" to this bit longer than 10s initiates a device reset
through the microprocessor interface. All internal circuits are
placed in the reset state with this bit set to a "1" except the micro-
processor register bits.
R/W
0
NOTE: Register Type Abrbreviation:
R = Read Only, R/W = Read or Write, RUR = Reset Upon Read
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