TABLE
參數(shù)資料
型號: XRT75R12DIB-L
廠商: Exar Corporation
文件頁數(shù): 98/133頁
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
標準包裝: 40
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 12/12
規(guī)程: DS3,E3,STS-1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 420-LBGA 裸露焊盤
供應商設備封裝: 420-TBGA(35x35)
包裝: 托盤
XRT75R12D
63
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 24: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR224 (ADDRESS LOCATION = 0XE0)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Channel 11
Interrupt
Enable
Channel 10
Interrupt
Enable
Channel 9
Interrupt
Enable
Channel 8
Interrupt
Enable
Channel 7
Interrupt
Enable
Channel 6
Interrupt
Enable
R/W
REGISTER - CR224 (ADDRESS LOCATION = 0XE0)
BIT
NUMBER
NAME
TYPE
DESCRIPTION
7,6
Reserved
5
4
3
2
1
0
Channel 11 Interrupt Enable
Channel 10 Interrupt Enable
Channel 9 Interrupt Enable
Channel 8 Interrupt Enable
Channel 7 Interrupt Enable
Channel 6 Interrupt Enable
R/W
Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
To enable Channel n for Interrupt Generation at the Channel
Level
To disable all Interrupts associated with Channel n within the
XRT75R12D
This is a "master" enable bit for each channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to the
Host via the INT pin.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
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