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XRT75R12D
70
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
TABLE 31: XRT75R12D REGISTER MAP SHOWING INTERRUPT STATUS REGISTERS (ISR_N) (N = [0:11])
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Change of FL
Condition
Interrupt Status
Ch_n
Change of LOL
Condition
Interrupt Status
Ch_n
Change of LOS
Condition
nterrupt Status
Ch_n
Change of DMO
Condition
Interrupt Status
Ch_n
RUR
SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM2 (M = 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7 - 4
Reserved
3
Change of FL Con-
dition Interrupt Sta-
tus
RUR
Change of FL (FIFO Limit Alarm) Condition Interrupt Status - Ch n:
This RESET-upon-READ bit-field indicates whether or not the Change of FL
Condition Interrupt (for Channel n) has occurred since the last read of this
register.
0 - Indicates that the Change of FL Condition Interrupt has NOT occurred
since the last read of this register.
1 - Indicates that the Change of FL Condition Interrupt has occurred since
the last read of this register.
NOTE:
The user can determine the current state of the FIFO Alarm
condition by reading out the contents of Bit 3 (FL Alarm Declared)
within the Alarm Status Register.(n)
2
Change of LOL Con-
dition Interrupt Sta-
tus
RUR
Change of Receive LOL (Loss of Lock) Condition Interrupt Status - Ch
n:
This RESET-upon-READ bit-field indicates whether or not the Change of
Receive LOL Condition Interrupt (for Channel n) has occurred since the last
read of this register.
0 - Indicates that the Change of Receive LOL Condition Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Change of Receive LOL Condition Interrupt has
occurred since the last read of this register.
NOTE: The user can determine the current state of the Receive LOL Defect
condition by reading out the contents of Bit 2 (Receive LOL Defect
Declared) within the Alarm Status Register.(n)