Although the role of the H1, H2 an" />
參數(shù)資料
型號： XRT75R12DIB-L
廠商： Exar Corporation
文件頁數(shù)： 131/133頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標準包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應商設備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12D
93
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
Although the role of the H1, H2 and H3 bytes will be discussed in much greater detail in “Section 8.3, Jitter/
Wander due to Pointer Adjustments” on page 101. For now, we will simply state that the role of these bytes
is two-fold.
To permit a given PTE (Path Terminating Equipment) that is receiving an STS-1 data to be able to locate the
STS-1 SPE (Synchronous Payload Envelope) within the Envelope Capacity of this incoming STS-1 data
stream and,
To inform a given PTE whenever Pointer Adjustment and NDF (New Data Flag) events occur within the
incoming STS-1 data-stream.
8.2.1.1.2
The Envelope Capacity Bytes within an STS-1 Frame
In general, the Envelope Capacity Bytes are any bytes (within an STS-1 frame) that exist outside of the TOH
bytes. In short, the Envelope Capacity contains the STS-1 SPE (Synchronous Payload Envelope). In fact,
every single byte that exists within the Envelope Capacity also exists within the STS-1 SPE.
The only
difference that exists between the "Envelope Capacity" as defined in Figure 40 and Figure 41 above and the
STS-1 SPE is that the Envelope Capacity is aligned with the STS-1 framing boundaries and the TOH bytes;
whereas the STS-1 SPE is NOT aligned with the STS-1 framing boundaries, nor the TOH bytes.
The STS-1 SPE is an "87 byte column x 9 row" data-structure (which is the exact same size as is the Envelope
Capacity) that is permitted to "float" within the "Envelope Capacity". As a consequence, the STS-1 SPE (within
an STS-1 data-stream) will typically straddle across an STS-1 frame boundary.
8.2.1.1.3
The Byte Structure of the STS-1 SPE
As mentioned above, the STS-1 SPE is an 87 byte column x 9 row structure. The very first column within the
STS-1 SPE consists of some overhead bytes which are known as the "Path Overhead" (or POH) bytes. The
remaining portions of the STS-1 SPE is available for "user" data. The Byte Structure of the STS-1 SPE is
presented below in Figure 42.
FIGURE 41. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME
A1
B1
D1
H1
B2
D4
S1
D10
D7
C1
F1
D3
H3
K2
D6
E2
D12
D9
A2
E1
D2
H2
K1
D5
M0
D11
D8
Envelope Capacity
Bytes
Envelope Capacity
Bytes
3 Byte Columns
87 Byte Columns
9 Rows
The TOH Bytes
相關(guān)PDF資料
PDF描述
XRT75R12IB-L IC LIU E3/DS3/STS-1 12CH 420TBGA
XRT75VL00DIV IC LIU E3/DS3/STS-1 1CH 52TQFP
XRT75VL00IV-F IC LIU E3/DS3/STS-1 1CH 52TQFP
XRT79L71IB-F IC LIU/FRAMER DS3/E3 1CH 208BGA
XRT81L27IV-F IC LIU EI 7CH 3.3V 128TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R12ES 功能描述:時鐘合成器/抖動清除器 12CH T3/E3/STS1LIUJA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R12IB 功能描述:外圍驅(qū)動器與原件 - PCI 12CH E3/DS3/STS W/JITTER R3 TECH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12IB-F 功能描述:外圍驅(qū)動器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12IB-L 功能描述:LIN 收發(fā)器 Attenuator RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT75VL00 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
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