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參數(shù)資料
| 型號： | XRT75R12DIB-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 79/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| 標準包裝： | 40 |
| 類型： | 線路接口裝置（LIU） |
| 驅動器/接收器數(shù)： | 12/12 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 420-LBGA 裸露焊盤 |
| 供應商設備封裝： | 420-TBGA（35x35） |
| 包裝： | 托盤 |
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XRT75R12D
III
REV. 1.0.3
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 24: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR224 (ADDRESS LOCATION = 0XE0)....................................................... 63
TABLE 25: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61) ......................................................... 64
TABLE 26: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR225 (ADDRESS LOCATION = 0XE1)....................................................... 65
TABLE 27: DEVICE/PART NUMBER REGISTER - CR110 (ADDRESS LOCATION = 0X6E) ........................................................................... 65
TABLE 28: CHIP REVISION NUMBER REGISTER - CR111 (ADDRESS LOCATION = 0X6F) ......................................................................... 66
THE PER-CHANNEL REGISTERS........................................................................................................................... 67
REGISTER DESCRIPTION - PER CHANNEL REGISTERS .................................................................................... 67
TABLE 29: XRT75R12D REGISTER MAP SHOWING INTERRUPT ENABLE REGISTERS (IER_N) (N = [0:11]).............................................. 67
TABLE 30: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL N ADDRESS LOCATION = 0XM1 .................................................... 68
TABLE 31: XRT75R12D REGISTER MAP SHOWING INTERRUPT STATUS REGISTERS (ISR_N) (N = [0:11]).............................................. 70
TABLE 32: XRT75R12D REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_N) (N = [0:11]) ..................................................... 72
TABLE 33: XRT75R12D REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_N) (N = [0:11]) ........................................... 76
TABLE 34: XRT75R12D REGISTER MAP SHOWING RECEIVE CONTROL REGISTERS (RC_N) (N = [0:11]) ............................................... 78
TABLE 35: XRT75R12D REGISTER MAP SHOWING CHANNEL CONTROL REGISTERS (CC_N) (N = [0:11]) .............................................. 80
TABLE 36: XRT75R12D REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_N) (N = [0:11]) ............................. 83
TABLE 37: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER MSBYTE REGISTERS (EM_N) (N = [0:11]).................................. 84
TABLE 38: ERROR COUNTER MSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMA (M = 0-5 & 8-D) ....................................... 84
TABLE 39: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER LSBYTE REGISTERS (EL_N) (N = [0:11])..................................... 84
TABLE 40: ERROR COUNTER LSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMB (M = 0-5 & 8-D) ........................................ 85
TABLE 41: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER HOLDING REGISTERS (EH_N) (N = [0:11])................................... 85
TABLE 42: ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC (M = 0-5 & 8-D) ....................................... 86
8.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ............................................................... 87
8.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 87
FIGURE 37. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ............... 88
8.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 89
8.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 89
FIGURE 38. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME ..................................................................................................... 90
FIGURE 39. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED
91
FIGURE 40. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 92
FIGURE 41. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 93
FIGURE 42. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE ............................................................................................. 94
FIGURE 43. AN ILLUSTRATION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE ......... 95
FIGURE 44. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO AN
STS-1 SPE.......................................................................................................................................................................... 95
8.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ......................................... 96
FIGURE 45. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE .................................... 97
FIGURE 46. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3 SIGNAL
THAT HAS A BIT RATE OF
44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL .................................................................................. 99
FIGURE 47. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL
THAT HAS A BIT RATE OF
44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL................................................................................. 100
8.3
JITTER/WANDER DUE TO POINTER ADJUSTMENTS ............................................................................ 101
8.3.1 THE CONCEPT OF AN STS-1 SPE POINTER......................................................................................................... 101
FIGURE 48. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES ......................................... 101
FIGURE 49. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION OF
THE
J1 BYTE, DESIGNATED .................................................................................................................................................. 102
FIGURE 50. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2 BYTES)
AND THE
LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME ................................................ 102
8.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK ................................................................................ 103
8.3.3 CAUSES OF POINTER ADJUSTMENTS ................................................................................................................. 103
FIGURE 51. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER.................................................................. 104
FIGURE 52. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS DES-
IGNATED
............................................................................................................................................................................. 105
FIGURE 53. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS DES-
IGNATED
............................................................................................................................................................................. 106
8.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ............................................................................. 107
8.4 CLOCK GAPPING JITTER ........................................................................................................................... 107
FIGURE 54. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION ...................................... 107
8.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE)
FOR DS3 APPLICATIONS .......................................................................................................................... 108
TABLE 43: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS ...... 108
8.5.1 DS3 DE-MAPPING JITTER....................................................................................................................................... 109
8.5.2 SINGLE POINTER ADJUSTMENT ........................................................................................................................... 109
FIGURE 55. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO ............................................................................................. 109
8.5.3 POINTER BURST...................................................................................................................................................... 110
相關PDF資料 |
PDF描述 |
|---|---|
| XRT75R12IB-L | IC LIU E3/DS3/STS-1 12CH 420TBGA |
| XRT75VL00DIV | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT75VL00IV-F | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| XRT79L71IB-F | IC LIU/FRAMER DS3/E3 1CH 208BGA |
| XRT81L27IV-F | IC LIU EI 7CH 3.3V 128TQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75R12ES | 功能描述:時鐘合成器/抖動清除器 12CH T3/E3/STS1LIUJA 3.3V W/REDUNDANCY RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75R12IB | 功能描述:外圍驅動器與原件 - PCI 12CH E3/DS3/STS W/JITTER R3 TECH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R12IB-F | 功能描述:外圍驅動器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75R12IB-L | 功能描述:LIN 收發(fā)器 Attenuator RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8 |
| XRT75VL00 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR |
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